Differences

This shows you the differences between two versions of the page.

--- start [2023/01/30 15:28]
rajit [ACT language]
+++ start [2024/02/22 17:45] (current)
fabian [ACT library]
@@ Line 3: / Line 3: @@
 Welcome to the Wiki for the ACT suite of VLSI design tools. ACT is an **A**synchronous **C**ircuit **T**oolkit which has been built from scratch to support the design and implementation of asynchronous logic. While that is the main goal, some of the tools we have developed have also been used for designing synchronous logic. These tools have been developed primarily by [[http://csl.yale.edu/~rajit/|Rajit Manohar]] and his [[http://avlsi.csl.yale.edu/|research group]], and have a long [[history:|history]].
+When an existing open-source tool used by mainstream chip designers can be re-purposed for asynchronous design without major issues (in terms of functionality as well as error-prone behavior), we re-use it. Examples include layout editors (e.g. ''magic''), switch-level simulators (e.g. ''irsim''), and analog simulators (e.g. ''Xyce'').
 ===== Asynchronous design =====
   * [[tutorial:|Tutorials and class materials]]
+  * [[asic:start|ACT ASIC flow]]
 ===== ACT language =====
@@ Line 18: / Line 20: @@
   * [[stdlib:|Standard library]]
-  * [[lib:|Using the ACT library]]
+  * [[sim:|Simulation library]], installed together with [[tools:actsim|actsim]]; It provides tools for simulation and verification
+  * [[http://avlsi.csl.yale.edu/act_docs/|Using the ACT library]] (work in progress!)
+  * [[guide:|Guide to using ACT data structures]]
 ===== Tools =====
   * [[stdoptions:|Command-line options]] and environment variables that are common for all core ACT tools
   * [[tools:|Individual tools]]
+  * [[asic:start|ASIC flow]]