Publications

The documents listed below are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

Programmable Substrates
Cross-cutting Projects
Older Projects
By Date: [click to toggle all]

Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, and Maya Gokhale. Designing an energy-efficient fully-asynchronous deep learning convolution engine. Late breaking results, Design Automation and Test in Europe (DATE), 2024.

Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, and Hai Helen Li. Neuro-symbolic computing: advancements and challenges in hardware-software co-design. IEEE Transactions on Circuits and Systems II (TCAS II), 2023.

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, and Rick Taylor. Toward Carbon-Aware Networking. ACM SIGENERGY Energy Informatics Review (EIR), October 2023.

Rajit Manohar and Yoram Moses. Timed Signaling Processes. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)   — Best paper award

Xiang Wu and and Rajit Manohar. Verification-driven Design for Asynchronous VLSI. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)


By Research Area

Neuroscience and Computing [click to toggle all]

Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf)

Design Methodology and Automation [click to toggle all]

Rajit Manohar and Yoram Moses. Timed Signaling Processes. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)   — Best paper award

Xiang Wu and and Rajit Manohar. Verification-driven Design for Asynchronous VLSI. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Karthi Srinivasan, Yoram Moses, and Rajit Manohar. Opportunistic Mutual Exclusion. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)   — Best paper nominee

Rajit Manohar. xcell: a library characterizer for combinational and state-holding gates. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2022. (pdf)

Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452--3465 (TCAD), October 2022. (pdf)

Energy-efficient VLSI [click to toggle all]

Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, and Maya Gokhale. Designing an energy-efficient fully-asynchronous deep learning convolution engine. Late breaking results, Design Automation and Test in Europe (DATE), 2024.

Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, and Hai Helen Li. Neuro-symbolic computing: advancements and challenges in hardware-software co-design. IEEE Transactions on Circuits and Systems II (TCAS), 2023.

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, and Rick Taylor. Toward Carbon-Aware Networking. ACM SIGENERGY Energy Informatics Review (EIR), October 2023.

Eve Schooler, Rick Taylor, Noa Zilberman, Robert Soulé, Dawn Nafus, Rajit Manohar, and Uri Cummings. A Perspective on Carbon-aware Networking. Internet Architecture Board Workshop on Environmental Impact of Internet Applications and Systems, December 2022. (pdf)

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, Rick Taylor. Toward Carbon-Aware Networking. HotCarbon 2022: 1st Workshop on Sustainable Computer Systems Design and Implementation, July 2022. (pdf)

Asynchronous FPGAs [click to toggle all]

Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf)

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.

Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf)

Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper nominee

Ultra Low Power Embedded Systems [click to toggle all]

Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf)

Asynchronous Computer Architecture [click to toggle all]

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé. Zerializer: Towards Zero-Copy Serialization. 18th Workshop on Hot Topics in Operating Systems (HotOS), May/June 2021. (abstract, pdf)

Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf)

Three Dimensional Integration [click to toggle all]

Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf)

T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract)

S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.

Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf)

David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf)

Resilient Asynchronous Systems [click to toggle all]

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf)

Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.

Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.

Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf)

Selected Technical Reports:

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12 from the Caltech Computer Science department.

Rajit Manohar and Paolo A.G. Sivilotti. Composing Processes Using Modified Rely-Guarantee Specifications. Caltech technical report CS-TR-96-22, November 1996.

Rajit Manohar. Folded FIFOs. Caltech technical report CS-TR-95-09, July 1995.

Issued Patents:

US Patent and Trademark Office search

Notes:

These are "scraps of paper" that are part of my research notes. Some of them turn into publications, but they all contain some idea that I thought was worth recording at the time. If you are interested in any of them (some of them have been cited by papers), send me e-mail.


Errata:
  • The paper on "Slack Elasticity" published in the proceedings of the conference on the Mathematics of Program Construction (1998) has an error in the final printed version due to an unfortunate oversight in proof-reading. Corollary 1 should read: If a system satisfies its specification when the slack on channel c is k, and if it is unchanged when the slack on channel c is l (> k), it satisfies its specification when the slack on c is s, for all s satisfying k <= s <= l. An examination of the proof shows that this is the statement being established, so the proof is identical. This statement was the version presented at the conference as well.
  • The paper on "AMC" published in ASYNC 2019 has an error in Figure 2 in the write completion circuitry. The p-stack should be powered with Vdd, the output is taken from the node between the n-fet and p-fets, and there is an input inverter on the wreq line. (Thanks to Matt Guthaus for pointing this out!)
  • The paper on "The impact of on-chip communication on memory technologies for neuromorphic systems" (and the equation replicated in the CICC overview) presents a simple model of spike queuing delay where the number of spikes is NR/2; this examines spikes generated in one second, and can be too conservative. Instead, one should select a time window dT where the queuing effect is considered, and the spike count would be NR*dT/2. This can change the absolute bandwidth required, depending on the choice of dT. dT has to determined by the worst-case spike queuing scenario for the architecture, and can reduce the bandwidth requirements by 10-100x. (Thanks to Bryce Primavera from NIST for requesting a clarification on the analysis.)


 
  
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