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--- asic:timing:start [2024/03/21 13:02]
rajit [Creating the timing graph]
+++ asic:timing:start [2024/03/21 13:38]
rajit [Creating the timing graph]
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-=== What edges should be ticked? ===
-This is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph.
-Let's consider a simple example of a handshake protocol between two processes shown below.
-{{ :asic:timing:tick_eg1a.png?600 |}}
-In this example, the handshake starts with the request going high (''req+''). This means that the ticked edge would be from ''ack-'' to ''req+'', since the ''i''th transition of ''ack-'' results in the ''(i+1)''th transition of ''req+''.
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