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asic:timing:start [2024/03/21 13:14] rajit [Creating the timing graph] |
asic:timing:start [2024/03/21 13:31] rajit [Creating the timing graph] |
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| This is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph. | This is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph. | ||
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| + | == Control logic == | ||
| Let's consider a simple example of a handshake protocol between two processes shown below. | Let's consider a simple example of a handshake protocol between two processes shown below. | ||
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| {{ : | {{ : | ||
| + | Basically the //first// transition that occurs when reset is released tends to have its input edges ticked. Ticks are fungible; if all the inbound edges to a vertex in the timing graph are ticked, that is equivalent (from a timing analysis perspective) to adding a tick to all the outbound edges from the vertex (and eliminating the inbound ticks). While in general an edge could have multiple ticks, Cyclone restricts its attention to timing graphs where each edge has at most one tick. (This can be worked around easily if needed.) | ||
| ==== Reading in parasitics ==== | ==== Reading in parasitics ==== | ||
| ===== Power ===== | ===== Power ===== | ||