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asic:timing:start [2024/03/21 13:25] rajit [Creating the timing graph] |
asic:timing:start [2024/03/22 16:03] rajit [Creating the timing graph] |
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==== Creating the timing graph ==== | ==== Creating the timing graph ==== | ||
- | There are two ways to create a timing graph. | + | There are two ways to create a timing graph: |
+ | - When the design is fully specified in ACT and production rules are specified using cells that are auto-extracted by the ACT tools (e.g. using the '' | ||
+ | - When the design has user-specified cells/black box cells, then ACT assumes that timing arcs could potentially relate any input pin of the cell to any output pin, and the arcs are computed based on those specified in the '' | ||
+ | Delays and transition times are added to the timing graph using information in the '' | ||
- | === Which edges should be ticked? === | ||
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- | This is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph. | ||
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- | == Control logic == | ||
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- | Let's consider a simple example of a handshake protocol between two processes shown below. | ||
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- | {{ : | ||
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- | In this example, the handshake starts with the request going high ('' | ||
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- | {{ : | ||