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history:start [2021/10/19 06:08] rajit |
history:start [2023/02/26 08:43] rajit |
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This is a rough chronology of the development/ | This is a rough chronology of the development/ | ||
+ | |||
+ | * 1975 E.W. Dijkstra' | ||
+ | * 1978 C.A.R. Hoare' | ||
+ | * 1986 A.J. Martin describes an approach to translating communicating processes into asynchronous circuits in a [[https:// | ||
* 1988-89: The [[https:// | * 1988-89: The [[https:// | ||
- | * ~1991 (?), a language for hierarchical production rules was developed at Caltech (A.J. Martin' | + | |
+ | Language development: | ||
+ | |||
+ | * ~1991 (?), a language for hierarchical production rules was developed at Caltech (A.J. Martin' | ||
+ | < | ||
+ | define prs (a)f() | ||
+ | { p -> q+ | ||
+ | | ||
+ | } | ||
+ | |||
+ | cell (_)f() | ||
+ | </ | ||
* 1995, a new CAST language ({{ : | * 1995, a new CAST language ({{ : | ||
* 1995-1998 CAST was used to implement the [[https:// | * 1995-1998 CAST was used to implement the [[https:// | ||
* ~1998 Andrew Lines and Uri Cummings from Martin' | * ~1998 Andrew Lines and Uri Cummings from Martin' | ||
- | * 1998-2003 CAST used at Cornell (Rajit Manohar' | + | * 1998-2003 CAST used at Cornell (Rajit Manohar' |
* 1998-2003 Development continued at Caltech, including embedding CAST-like syntax within the Modula-3 language. This version was used to design the Lutonium processor. | * 1998-2003 Development continued at Caltech, including embedding CAST-like syntax within the Modula-3 language. This version was used to design the Lutonium processor. | ||
* 2004 A language that provided the same functionality as CAST but with syntax for new features (not implemented) was developed at Cornell by Rajit Manohar, based on lessons from using CAST for chip design. This was called ACT (version 0; 0 because the new features were not supported yet) | * 2004 A language that provided the same functionality as CAST but with syntax for new features (not implemented) was developed at Cornell by Rajit Manohar, based on lessons from using CAST for chip design. This was called ACT (version 0; 0 because the new features were not supported yet) | ||
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* 2011, initial template for the core language based on ACT v0 developed | * 2011, initial template for the core language based on ACT v0 developed | ||
* 2012, Intel acquires Fulcrum Microsystems, | * 2012, Intel acquires Fulcrum Microsystems, | ||
- | * 2017, actual implementation of the new features started | + | * 2017, actual implementation of the new features started |
* 2018, Most features of ACT v1 ready | * 2018, Most features of ACT v1 ready | ||
- | * 1/2019, first open-source release | + | * 1/2019, first [[http:// |
* 4/2019, documentation effort initiated | * 4/2019, documentation effort initiated | ||
+ | |||
+ | Tool development: | ||
+ | |||
+ | * 1990-1995, Caltech point-tools for a number of tasks, including cell generation, placement, routing, and simulation. production rule generation, etc. | ||
+ | * 1995-1998, Scalability improvements for simulation, and translation of CAST language to interoperate with previous Caltech tools and newly developed tools including layout checks against production rules and a new implementation of SPICE. | ||
+ | * 1998-2010?, in-house tools developed by Fulcrum Microsystems | ||
+ | * 1999, new implementation of '' | ||
+ | * 2005, ACT tools to convert ACT info formats accepted by existing asynchronous design tools | ||
+ | * 2008, new co-simulation tools to leverage commercial simulations and integrate them with asynchronous circuit simulation | ||
+ | * 2017, new tools effort started | ||
+ | * 2020, support for LEF/DEF exports | ||
+ | * 2020, first prototype of '' | ||
+ | * 2020-2021, external optimization using open-source logic synthesis tools ('' | ||
+ | * 2020-2022, placement and routing flow developed | ||
+ | * 2020-2022, dataflow synthesis flow developed | ||
+ | * 2021-2023, timing-driven flow in development |