The ACT VLSI design tools

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asic:cells:start
asic:timing:xcell:start
intro_example:cadence_import
intro_example:start
language:langs:prs
scratch:configtut
start
stdoptions:start
tools:actsim
tools:netgen

config/start.txt · Last modified: 2025/08/01 12:39 by rajit

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