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asic:cells:start [2023/11/23 12:02] rajit created |
asic:cells:start [2024/08/23 10:03] (current) rajit |
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| For the ASIC flow, each production rule in the design is mapped to a //cell//. Cells are simply special processes that are used to specify the //leaf cells// in the layout generation flow. ACT assumes that each cell has associated with it some layout and an associated LEF file. Cells are specified using the same syntax as a process, but using '' | For the ASIC flow, each production rule in the design is mapped to a //cell//. Cells are simply special processes that are used to specify the //leaf cells// in the layout generation flow. ACT assumes that each cell has associated with it some layout and an associated LEF file. Cells are specified using the same syntax as a process, but using '' | ||
| - | ===== Cell libraries and mapping | + | ===== From production rules to cells ===== |
| Given that different asynchronous circuit families use different types of gates, the ACT ASIC flow assumes that the production rules that have been specified must be implemented as-is: in other words, any technology mapping step to a group of standard cells has been handled by logic synthesis. | Given that different asynchronous circuit families use different types of gates, the ACT ASIC flow assumes that the production rules that have been specified must be implemented as-is: in other words, any technology mapping step to a group of standard cells has been handled by logic synthesis. | ||