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--- asic:timing:forks [2024/02/02 11:52] – [Point-of-divergence constraint] rajit
+++ asic:timing:forks [2024/09/03 14:06] (current) – [Relative timing] rajit
@@ Line 26: / Line 26: @@
 There are many closely related but slightly different notions that are used in the literature to
-describe timing constraints in a variety of circuit contexts.
+describe timing constraints in a variety of circuit contexts.  Here we try and provide a simplified view of the differences and similarities between some common notions and timing forks.
 ==== Setup and hold time ====
@@ Line 50: / Line 50: @@
 ==== Relative timing ====
+Relative timing is a methodology for designing asynchronous circuits where you can assume that
+two signal transitions are ordered due to timing. When you assume that ''a+'' occurs before ''b-'' for example,
+there is an implicit assumption that ''a+'' and ''b-'' occur, and the methodology is most commonly used to reason about control logic where this is a common scenario.
+Timing fork theory states that if the two transitions are guaranteed to be ordered, then a timing fork/zig-zag that is the basis for the ordering must exist.  In other words, a design that uses relative timing constraints can only be correct if a timing fork/zig-zag exists that ensures that the constraint is satisfied.
+It is worth noting that a timing fork doesn't //require// that all the transitions occur. This is useful when we have data-dependent timing constraints, i.e., where a signal change occurs only in certain cases based data values being computed by the circuit.