Differences

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--- asic:timing:start [2024/08/16 18:18] – [Loading in the timer] rajit
+++ asic:timing:start [2024/08/19 12:32] (current) – [Timing] rajit
@@ Line 11: / Line 11: @@
    * [[asic:timing:constraints|Timing constraints]]
-Note that timing analysis requires that the design has been mapped to [[asic:cells:start|cells]].
+Note that timing analysis requires that the design has been mapped to [[asic:cells:start|cells]], and these
+cells have been [[asic:timing:xcell:start|characterized]] using extensive circuit simulations that are summarized in a Liberty file.
 ==== Loading the timer ====
@@ Line 61: / Line 62: @@
 </code>
 Notice that we have passed in the handle corresponding to the Liberty file ''mylib.lib''.
+=== Scripting changes to the timing graph ===
+Sometimes it is useful to be able to edit the timing graph constructed by ACT. This can happen if, for example, the default timing graph generation algorithm doesn't produce the correct timing graph, or is too conservative. Also, this can occur if the ACT design doesn't include all the timing constraints or all the ticked edges.
+In the simple example earlier, ''timer:init'' built the timing graph using ACT and the Liberty file. In order to modify the timing graph and introduce new constraint checks, the timer initialization can be broken down into two steps: (i) constructing a timing graph using the ACT specification only; and (ii) incorporating timing arc information from the Liberty file. Between steps (i) and (ii), additional commands can be used to modify the timing graph.
+To build the timing graph, use:
+<code>
+interact> timer:build-graph
+</code>
+Once the timing graph exists, we can introduce additional ticked edges as follows:
+<code>
+interact> timer:tick a+ b-
+</code>
+This looks for a timing arc/edge from ''a+'' to ''b-'' , and ensures that the edge is ticked.
+New timing constraints can also be introduced:
+<code>
+interact> timer:add-constraint a+ b- c+
+</code>
+This command introduces a timing fork with ''a+'' as the root, ''b-'' as the fast tine of the fork, and ''c+'' as the slow tine of the fork.
+^ Command ^ Meaning  ^
+| timer:build-graph | Construct a timing graph from the ACT design only. |
+| timer:tick <net1>+/- <net2>+/-  | If the timing edge between the specified net transition exists, then the edge is ticked in the timing graph. |
+| timer:add-constraint <root>+/- [*]<fast>[+/-] [*]<slow>[+/-] [margin] | This adds a timing fork. The root of the fork must include a direction (''+'' or ''-''). A timing margin can also be specified. The syntax ''*'' is used to indicate that the event of interest is from the //next iteration// of the circuit relative to the root. |
+| timer:init <lh1> <lh2> ... <lhN> | This initializes the timing engine (including creating the timing graph if necessary) using the Liberty file handles <lh1> through <lhN>. Multiple Liberty files are used to specify different corners, etc.  |
+==== Running the timer ====
 At this point the timer can be run using:
@@ Line 70: / Line 104: @@
    * The unfolding factor ''M''.
 (For details about what this means, please read the [[asic:timing:graph|timing introduction]].)
+^ Command ^ Meaning  ^
+| timer:run  | Runs timing analysis on the design. This command returns a list ''(p M)'', where ''p'' is the cycle period and ''M'' is the unfolding factor. |
+==== Queries ====
+Once the run command is complete, a number of queries can be used to interrogate the computed timing.  To see the critical cycle in the design, use
+<code>
+interact> timer:crit
+</code>
+Timing information for a net can be viewed using
+<code>
+interact> timer:info a.b.signal
+</code>
 ==== Reading in parasitics ====
 ===== Power =====