Differences

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--- asic:timing:start [2024/08/16 18:37] – [Running the timer] rajit
+++ asic:timing:start [2024/08/19 12:32] (current) – [Timing] rajit
@@ Line 11: / Line 11: @@
    * [[asic:timing:constraints|Timing constraints]]
-Note that timing analysis requires that the design has been mapped to [[asic:cells:start|cells]].
+Note that timing analysis requires that the design has been mapped to [[asic:cells:start|cells]], and these
+cells have been [[asic:timing:xcell:start|characterized]] using extensive circuit simulations that are summarized in a Liberty file.
 ==== Loading the timer ====