Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | |||
| asic:timing:start [2024/08/19 12:31] – [Timing] rajit | asic:timing:start [2024/08/19 12:32] (current) – [Timing] rajit | ||
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| Note that timing analysis requires that the design has been mapped to [[asic: | Note that timing analysis requires that the design has been mapped to [[asic: | ||
| - | cells have been characterized using extensive circuit simulations that are summarized in a Liberty file. | + | cells have been [[asic: |
| ==== Loading the timer ==== | ==== Loading the timer ==== | ||