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--- asic:timing:xcell:start [2024/05/31 19:17] – [Configuration file] rajit
+++ asic:timing:xcell:start [2024/06/03 16:40] (current) – [Cells with external SPICE netlists and user-defined scenarios] rajit
@@ Line 90: / Line 90: @@
 </code>
+==== Cells with external SPICE netlists and user-defined scenarios ====
+The following is an example of a cell that needs special support for characterization.
+<code>
+begin cells
+   # the full ACT name of the cell
+   begin ::syn::var_one_bit<f>
+   # for an external netlist, uncomment the next line
+   # string spice "mycell.sp"
+   # characterization arcs
+    begin scenario
+   # scenario format
+   #   input-pin#     (0,1,...#inputs-1)
+   #   in_init_value  (0/1)
+   #   output-pin#    (0,1,...#outputs-1)
+   #   out_init_value  (0/1)
+   #   length         (2,3, or 4: length of scenario)
+   #   state1         (input truth-table format encoded as an integer)
+   #   state2
+   #   ...
+   #   stateN
+   int_table dynamic 0 0 0 0 3 2 0 1 \
+0 1 1 3 2 0 1 \
+0 0 1 3 1 0 2 \
+0 1 0 3 1 0 2
+   string_table function "wt*!wf*!Reset + !wt*!wf*!Reset*dt"  \
+                         "wf*!wt*!Reset + !wt*!wf*!Reset*df"
+   end
+   end
+end
+</code>
+The ''dynamic'' table specifies the scenarios to be run through for characterization. Each scenario corresponds to applying an input vector and running a SPICE simulation for the pre-specified amount. Scenarios can be of length 2, 3, or 4. For example, a simple combinational gate would have a scenario of length two:
+   * Step 1: apply an input vector to set the output vector to say zero.
+   * Step 2: change one of the inputs to cause the output to make a zero to one transition.
+(State-holding gates can require more complex scenarios for characterization.)
+The input vector is specified as an unsigned integer that corresponds to the values of all the input bits. The order is the same order as in the SPICE cell corresponding to subcircuit for the cell generated by ACT (e.g the same output order as you would find by running ''[[tools:netgen|prs2net]]''). To set input 0 to 1, 1 to 1, 2 to 0 would correspond to the bit pattern ''011'' (lab = bit 0), and hence the integer 3.