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--- config:expropt [2025/05/27 22:56] – karthi
+++ config:expropt [2025/05/28 01:09] (current) – [Liberty Files] karthi
@@ Line 1: / Line 1: @@
-====== Synthesis configuration ======
+====== Expression Synthesis Configuration ======
-The synthesis section of the configuration file specifies options for circuit synthesis in general. In particular, it has options for the expression optimizer, which is the interface between the ACT tool-suite and external logic synthesis tools, such as ABC.
+The synthesis section of the configuration file specifies options for circuit synthesis in general. In particular, it has options for the expression optimizer (expropt), which is the interface between the ACT tool-suite and external logic synthesis tools, such as ABC.
 We use these external tools to perform synthesis of expressions into combinational logic by emitting Verilog files which correspond to a logical expression, running the synthesis tool to get a mapped Verilog file, and converting that back to an ACT netlist.
@@ Line 22: / Line 22: @@
 </code>
-The ''max_power'' corner is the liberty file corresponding to the maximum power corner, which is usually the FF, high-temperature corner. The ''min_delay'' corner is the liberty file corresponding to the minimum delay corner, which is usually the FF, low-temperature corner.The ''max_delay'' corner is the liberty file corresponding to the maximum delay corner, which is usually the SS, high-temperature corner.
+The ''max_power'' corner is the liberty file corresponding to the maximum power corner, which is usually the FF, high-temperature corner. The ''min_delay'' corner is the liberty file corresponding to the minimum delay corner, which is usually the FF, low-temperature corner. The ''max_delay'' corner is the liberty file corresponding to the maximum delay corner, which is usually the SS, high-temperature corner.
 ===== QDI Cells =====
+For synthesis of a QDI datapath, we simply replace the definitions of the standard cells in the netlist with the corresponding QDI variant. This section (''qdi'') contains information about the QDI standard cells that are used.
+<code>
+string cell_lib "${ACT_HOME}/act/syn/qdi/stdcells.act"
+</code>
+The location of the QDI standard cells for this technology. These must correspond to the cells provided in the liberty files for the technology above.
+<code>
+string cell_lib_namespace "syn"
+</code>
+The full name of the ACT namespace within which the cells are defined.
+<code>
+string cell_lib_wire_type "dualrail"
+</code>
+The typename of the wire encoding that is used. In this case ''dualrail'' represents the fact that each wire/bool is represented as a ''dualrail'' in this circuit family.
 ===== Bundled Data Cells =====
+This section (''bundled'') contains information about the bundled-datapath standard cells that are used.
+<code>
+string cell_lib "${ACT_HOME}/act/std/cells.act"
+</code>
+The location of the standard cells for this technology. These must correspond to the cells provided in the liberty files for the technology above.
+<code>
+string cell_lib_namespace "std::cells"
+</code>
+The full name of the ACT namespace within which the cells are defined.
+<code>
+string cell_lib_wire_type "bool"
+</code>
+The typename of the wire encoding that is used. In this case, it is simply ''bool'' since each wire/bool is represented directly by itself.
 ===== Expression Optimizer Options =====
@@ Line 32: / Line 64: @@
 This section is within a pair of ''begin expropt'' and ''end'' blocks and contains options for the expression optimizer.
-==== Cache Configuration ====
+<code>
+int clean_tmp_files 1
+</code>
+This option deletes temporary files that are generated during expression synthesis such as the behavioral Verilog file that is passed in to the synthesis tool, the resultant mapped verilog file, log files etc. Set to 0 to keep these files.
-This section (''cache'') contains the location of the expression caches, which contained mapped verilog netlists corresponding to arithmetic/logic expressions for this technology. There are two cache locations - global and local. The global cache must be set. A typical location would be a folder within your ''ACT_HOME''.
+<code>
+int verbose 1
+</code>
+Defines the output verbosity for expropt. Set to 0 for no output on ''stdout'', 1 for dots, 2 for full dump of commands that are being run internally.
+<code>
+int skip_verification 0
+</code>
+For genus only. Set to 1 to skip verification with ''lec''.
+<code>
+int synthesis_effort 2
+</code>
+For genus only. Set the synthesis effort level: 0 for low, 1 for medium, 2 for high. The default value is 2.
+<code>
+int vectorize_all_ports 0
+</code>
+When the Verilog file is printed out for mapping, variables of bitwidth 1 are printed with as a single ''wire'' type, but all larger bitwidths are printed as wire arrays, such as ''wire [7:0]''. This may lead to incompatibility with other tools that use the output of expropt, and expect the ports of the process to always contain arrays of bools and not single bools. Setting this option to 1 will print single wires as ''wire [0:0]'' instead.
+<code>
+string driving_cell LATCH
+</code>
+Set the driving cell for static timing analysis of the mapped combinational gate-level netlist.
+<code>
+real default_load 8.7
+</code>
+Set the default load capacitance on the output of a gate, for static timing analysis of the mapped combinational gate-level netlist. The default value is 1.0.
+<code>
+real dynamic_power_period 10e-9
+</code>
+Logic synthesis tools report dynamic power assuming a certain clock frequency. This is the clock period. Default is 100 MHz, or 10ns.
+<code>
+string captable "/path/to/file/"
+</code>
+The captable for the technology (optional). Use white space to separate files inside the string. **TODO**
+<code>
+string lef "/path/to/file"
+</code>
+The LEF file for the technology + lib  (optional). Use white space to separate files inside the string. If the tech-LEF is separate, it has to be the first file. **TODO**
+==== ABC Options ====
+<code>
+begin abc
+  int use_constraints 1
+end
+</code>
+This only option in this section, currently, which instructs ABC to use the ''set_load'' and ''set_driving_cell'' constraints for STA, which are printed out into a ''constraints.sdc'' file, according to the configuration specified above.
+==== Genus Options ====
+==== Expression Cache Configuration ====
+This sub-section (''cache'') within the ''expropt'' section contains the location of the expression caches, which contained mapped verilog netlists corresponding to arithmetic/logic expressions for this technology. There are two cache locations - global and local. The global cache location must be set. A typical location would be a folder within your ''ACT_HOME''.
 <code>
 string global "${ACT_HOME}/shared_cache/expropt/generic"
@@ Line 49: / Line 142: @@
 </code>
 The ''invalidate'' option erases the entire cache for this technology when the expression optimizer starts up.