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| custom:start [2020/12/02 06:00] – external edit 127.0.0.1 | custom:start [2023/04/25 10:31] (current) – rajit |
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| * Circuit design. This is done via text entry using an [[language:start|ACT]] file. In this file you can specify pull-up and pull-down networks as well as transistor sizes (width/length) and type (e.g. low threshold, high threshold). | * Circuit design. This is done via text entry using an [[language:start|ACT]] file. In this file you can specify pull-up and pull-down networks as well as transistor sizes (width/length) and type (e.g. low threshold, high threshold). |
| * This circuit can be converted into a spice netlist using the ''netgen'' tool for analog simulation. This converts a hierarchical ACT design into a hierarchical spice netlist. | * This circuit can be converted into a spice netlist using the ''prs2net'' tool for analog simulation. This converts a hierarchical ACT design into a hierarchical spice netlist. |
| * This circuit can be simulated using existing switch-level simulators like ''irsim'' or ''cosmos'' using ''prs2sim'', which converts the hierarchical ACT design into a flat simulation file (''.sim'' and ''.al'') that can be read by ''irsim''/''cosmos''. | * This circuit can be simulated using existing switch-level simulators like ''irsim'' or ''cosmos'' using ''prs2sim'', which converts the hierarchical ACT design into a flat simulation file (''.sim'' and ''.al'') that can be read by ''irsim''/''cosmos''. |
| * Asynchronous gate-level simulation can be done using the ''prsim'' tool. | * Asynchronous gate-level simulation can be done using the ''prsim'' tool. |