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intro_example:inverter [2020/04/29 14:38] rajit |
intro_example:inverter [2022/05/13 09:15] (current) rajit |
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An inverter is a very simple process that has a one-bit digital input and one bit digital output. The following specifies a process that corresponds to one inverter. | An inverter is a very simple process that has a one-bit digital input and one bit digital output. The following specifies a process that corresponds to one inverter. | ||
- | < | + | < |
defproc inverter (bool? i; bool! o) | defproc inverter (bool? i; bool! o) | ||
{ | { | ||
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Let's start with the statements | Let's start with the statements | ||
- | < | + | < |
i -> o- | i -> o- | ||
~i -> o+ | ~i -> o+ | ||
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This is a combinational gate, which means either the pull-up or pull-down network is always conducting (alternatively, | This is a combinational gate, which means either the pull-up or pull-down network is always conducting (alternatively, | ||
- | < | + | < |
defproc inverter (bool? i; bool! o) | defproc inverter (bool? i; bool! o) | ||
{ | { | ||
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This fragment of ACT simply defines a process named '' | This fragment of ACT simply defines a process named '' | ||
- | < | + | < |
inverter inv; | inverter inv; | ||
</ | </ | ||
- | What can we do with this ACT file? The simplest thing is to simulate the inverter using a production-rule simulator. We have provided '' | + | Next, we can simulate the inverter using a production-rule simulator. We have provided '' |
+ | |||
+ | ===== Simulating with prsim ===== | ||
+ | |||
+ | The complete example is: | ||
+ | |||
+ | <code act> | ||
+ | defproc inverter (bool? i; bool! o) | ||
+ | { | ||
+ | prs { | ||
+ | i => o- | ||
+ | } | ||
+ | } | ||
+ | |||
+ | inverter inv; | ||
+ | </ | ||
+ | |||
+ | |||
+ | If the file above is called '' | ||
+ | |||
+ | < | ||
+ | % aflat test_inv.act > test_inv.prs | ||
+ | </ | ||
+ | |||
+ | The output file is the following: | ||
+ | |||
+ | < | ||
+ | " | ||
+ | ~" | ||
+ | </ | ||
+ | |||
+ | Note that ACT uses '' | ||
+ | |||
+ | If the file is saved as '' | ||
+ | |||
+ | < | ||
+ | % prsim test_inv.prs | ||
+ | |||
+ | (Prsim) initialize | ||
+ | (Prsim) watch inv.i | ||
+ | (Prsim) watch inv.o | ||
+ | (Prsim) status X | ||
+ | (Prsim) set inv.i 0 | ||
+ | (Prsim) cycle | ||
+ | (Prsim) set inv.i 1 | ||
+ | (Prsim) cycle | ||
+ | </ | ||
+ | |||
+ | '' | ||
+ | |||
+ | One of the useful features of '' | ||
+ | |||
+ | < | ||
+ | (Prsim) random | ||
+ | </ | ||
+ | |||
+ | After this command, all delays are randomized. This is a useful test to see if your production rules are stable and non-interfering. If '' | ||