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intro_example:start [2025/05/17 11:56] – [Connections] rajitintro_example:start [2025/05/22 10:01] (current) – [Organizing your design] rajit
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 ACT supports the description of circuits are multiple levels of abstraction in a unified framework. Details of the language can be found in the [[language:start|detailed language description]]. The examples provided below are a gentler introduction to various language features, and may be easier to follow than the language description itself. ACT supports the description of circuits are multiple levels of abstraction in a unified framework. Details of the language can be found in the [[language:start|detailed language description]]. The examples provided below are a gentler introduction to various language features, and may be easier to follow than the language description itself.
  
-===== Simple circuit examples =====+===== Circuit examples =====
  
 ACT can describe circuits are multiple levels of abstraction. At the highest level of abstraction, circuits ACT can describe circuits are multiple levels of abstraction. At the highest level of abstraction, circuits
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   * Dependent [[template_deps|templates]]   * Dependent [[template_deps|templates]]
   * Using [[standard_sim|standard testing environments]]   * Using [[standard_sim|standard testing environments]]
- +  * More on [[connection_info|connections]] and how they work
- +
-Apart from variables used for parameters (e.g. ''pint'' variables), all variables in ACT correspond to +
-names for circuit components/wires. So the instance ''one_place_buffer b;''  +
-creates the variable ''b'' that is used to refer to all the elements of the circuit component defined by a new ''one_place_buffer'' process. Connecting two variables makes them refer to the same circuit element. Connecting two processes makes the two variables correspond to one process, and connecting two channels makes them the same channel. The two connected variables can be viewed as aliases, i.e. different ways to refer to the same process. +
- +
-ACT provides flexible syntax for connections between circuit variables, and the examples below illustrate some common use cases: +
   * [[loops|Loops]] and selections   * [[loops|Loops]] and selections
   *Other ways to write the [[intro_example:chp_fifo2|buffer example]]   *Other ways to write the [[intro_example:chp_fifo2|buffer example]]
 +  * [[assertions|Assertions]] in parameterized definitions
 +  * [[name_mangling|Expanded names]] in ACT
 +  * Using [[.pure_struct|pure structures]]
 +  * Defining [[.operators|operators]]
  
-===== Pure structures ===== 
- 
-[[language:types2:data#pure_structures|Pure structures]] are user-defined data types that can be used to group related values (like ''struct'' in C/C++). 
- 
-   * Using [[.pure_struct|pure structures]] 
-   * Defining [[.operators|operators]] 
 ===== Organizing your design ===== ===== Organizing your design =====
  
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   * Creating [[namespace|libraries and namespaces]]   * Creating [[namespace|libraries and namespaces]]
 +  * Organizing your [[files|files]]
   * Tracking [[dependencies|dependencies]] between ACT files   * Tracking [[dependencies|dependencies]] between ACT files
  
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 ===== Low-level circuit design and SPICE simulation ===== ===== Low-level circuit design and SPICE simulation =====
  
-So far we have learned how to describe a circuit in ACT, simulate using prsim and irsim. Now, we will move on to the next stage i.e. designing CMOS circuits from ACT description. The process of designing circuit often starts with creating a spice netlist to simulate transistor-level circuit behavior. In order to generate a spice netlist, ACT requires some technology-dependent information and information to understand designer’s intent. We use configuration files to provide such information. For more information on configuration files, see [[config:start|ACT configuration files]]+So far we have learned how to describe a circuit in ACT, simulate using actsim, prsim and irsim. Now, we will move on to the next stage i.e. designing CMOS circuits from ACT description. The process of designing circuit often starts with creating a spice netlist to simulate transistor-level circuit behavior. In order to generate a spice netlist, ACT requires some technology-dependent information and information to understand designer’s intent. We use configuration files to provide such information. For more information on configuration files, see [[config:start|ACT configuration files]]
  
 The configuration files are saved in ''$ACT_HOME/conf/<technology>/'' directory. The default technology is called ''generic'', and the default configuration options are in ''global.conf''. It is possible to save technology specific configuration for each tool in a separate configuration file. For example, ''prs2net.conf'' for configuration related to netlist generator and ''layout.conf'' for layout parameters. The configuration files are saved in ''$ACT_HOME/conf/<technology>/'' directory. The default technology is called ''generic'', and the default configuration options are in ''global.conf''. It is possible to save technology specific configuration for each tool in a separate configuration file. For example, ''prs2net.conf'' for configuration related to netlist generator and ''layout.conf'' for layout parameters.
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    * Specifying transistor [[sizing|sizes]] for CMOS implementation    * Specifying transistor [[sizing|sizes]] for CMOS implementation
    * Generating spice [[netlist|netlist]] and simulation with [[https://xyce.sandia.gov/about_xyce/index.html|Xyce]]    * Generating spice [[netlist|netlist]] and simulation with [[https://xyce.sandia.gov/about_xyce/index.html|Xyce]]
 +   * [[name_mangling|Name mangling]] in ACT
 ===== External tools ===== ===== External tools =====
  
intro_example/start.1747482967.txt.gz · Last modified: 2025/05/17 11:56 by rajit
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