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language:langs:spec [2026/06/14 13:41] – [Simulation directives] rajitlanguage:langs:spec [2026/06/14 13:41] (current) – [Timing directives] rajit
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 The directive ''rand_init'' is used to let the simulator know that a signal might be undefined on power-up, but will initialize to either 0 or 1 at random. The directive ''hazard'' is used to let the simulator know that a particular signal can have a switching hazard. The directive ''rand_init'' is used to let the simulator know that a signal might be undefined on power-up, but will initialize to either 0 or 1 at random. The directive ''hazard'' is used to let the simulator know that a particular signal can have a switching hazard.
  
-==== Timing directives ====+===== Timing directives =====
  
 There are two types of timing directives: constraints, and tick specifiers on timing edges. There are two types of timing directives: constraints, and tick specifiers on timing edges.
  
-=== Tick specifiers ===+==== Tick specifiers ====
  
 Asynchronous circuits oscillate, and each oscillation can be viewed as an iteration of the circuit. For [[asic:timing:graph|timing analysis]], it is important to indicate connections from one iteration to the next---i.e. when a signal transition from the current indication leads to a transition from the next iteration. Such directives can be computed during logic synthesis, and ACT expects all logic synthesis tools to emit these directives along with the gate-level implementation.  Asynchronous circuits oscillate, and each oscillation can be viewed as an iteration of the circuit. For [[asic:timing:graph|timing analysis]], it is important to indicate connections from one iteration to the next---i.e. when a signal transition from the current indication leads to a transition from the next iteration. Such directives can be computed during logic synthesis, and ACT expects all logic synthesis tools to emit these directives along with the gate-level implementation. 
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 This says all edges leaving ''s-'' must be ticked. The syntax uses the ''?'' prefix, and the signal transition on the two sides of the arrow must be the same. This says all edges leaving ''s-'' must be ticked. The syntax uses the ''?'' prefix, and the signal transition on the two sides of the arrow must be the same.
  
-=== Timing constraints ===+==== Timing constraints ====
  
 Timing constraints in ACT are specified using [[asic:timing:forks|timing forks]]. Timing forks are used to specify a point of divergence relative timing constraint. The constraint  Timing constraints in ACT are specified using [[asic:timing:forks|timing forks]]. Timing forks are used to specify a point of divergence relative timing constraint. The constraint 
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 </code> </code>
 This has the same meaning as the earlier fork, except that the tools are provided with a hint that says that it is okay to add delays to correct any violations of this fork. This has the same meaning as the earlier fork, except that the tools are provided with a hint that says that it is okay to add delays to correct any violations of this fork.
- 
- 
  
 Finally, timing forks may relate transitions from adjacent iterations.  Finally, timing forks may relate transitions from adjacent iterations. 
- 
 <code act> <code act>
 spec { spec {
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 The ''*'' indicates that the ''b-'' transition is from the following iteration. The ''*'' indicator can appear on any signal except the root of the timing fork (in this case ''a+''). The ''*'' indicates that the ''b-'' transition is from the following iteration. The ''*'' indicator can appear on any signal except the root of the timing fork (in this case ''a+'').
  
-=== Deleting timing edges ===+==== Deleting timing edges ====
  
 When computing conservative approximations to timing graphs, ACT may add extra edges to the timing graph that are in fact not present in the true timing graph for the system. This can occur, for example, when a gate is modified to incorporate extra signals to simplify the circuit implementation but the new input has no bearing on event causality in the asynchronous circuit. If the automated timing graph construction algorithm includes such edges, they can be explicitly deleted using the following directive: When computing conservative approximations to timing graphs, ACT may add extra edges to the timing graph that are in fact not present in the true timing graph for the system. This can occur, for example, when a gate is modified to incorporate extra signals to simplify the circuit implementation but the new input has no bearing on event causality in the asynchronous circuit. If the automated timing graph construction algorithm includes such edges, they can be explicitly deleted using the following directive:
language/langs/spec.txt · Last modified: by rajit
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