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language:langs:start [2022/06/24 06:44] rajit [Sub-languages to specify circuits] |
language:langs:start [2022/07/11 07:43] (current) rajit [Auxillary sub-languages] |
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- | When simulating a design or translating the circuit to an implementation, | + | When simulating a design or translating the circuit to an implementation, |
The CHP sub-language is used to describe the circuits using a programming notation. The HSE sub-language operates on Boolean-valued variables, and has syntax similar to the CHP block. A process can have at most one CHP block and at most one HSE block; if multiple blocks of the same type are detected, an error will be flagged. | The CHP sub-language is used to describe the circuits using a programming notation. The HSE sub-language operates on Boolean-valued variables, and has syntax similar to the CHP block. A process can have at most one CHP block and at most one HSE block; if multiple blocks of the same type are detected, an error will be flagged. | ||
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* [[refine|Refinement]]: | * [[refine|Refinement]]: | ||
- | The refinement body is simply a standard ACT body. When the refinement body is selected, the other circuit languages are omitted. Similarly when one of CHP/HSE/PRS are selected, the refinement body is omitted. | + | The refinement body is simply a standard ACT body. When the refinement body is selected, the other circuit languages are omitted. Similarly when one of CHP/HSE/PRS are selected, the refinement body is omitted. The refinement body can be selected using the '' |
- | ===== Auxillary | + | ===== Auxiliary |
+ | |||
+ | Auxiliary sub-languages augment the circuit specification in some way. The sizing sub-language can be used to specify gate sizing directives that apply to the '' | ||
* [[sizing|Gate sizing directives]] | * [[sizing|Gate sizing directives]] | ||
* [[spec|Specifications]] | * [[spec|Specifications]] | ||
+ | ===== Selecting sub-language level ===== | ||
+ | |||
+ | There are four possible levels of detail at which to model a circuit component: | ||
+ | * CHP, where channels and full expression syntax is permitted | ||
+ | * HSE, where sequencing can be specified, but all variables are Boolean-valued | ||
+ | * PRS, which corresponds to individual pull-up and pull-down networks (gates) | ||
+ | * device, which corresponds to the transistor-level implementation of the gates. The device level doesn' | ||
+ | |||
+ | A configuration file can be specified that selects the level of detail for a process | ||
+ | |||
+ | < | ||
+ | begin level | ||
+ | # valid strings are " | ||
+ | | ||
+ | end | ||
+ | </ | ||
+ | This specifies the default level selected for every process. (Dataflow is treated as fine-grained parallel CHP.) | ||
+ | |||
+ | < | ||
+ | begin level | ||
+ | begin types | ||
+ | # chp process model | ||
+ | | ||
+ | # prs process model | ||
+ | | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | This specifies that the particular process names should be modeled at the specified level of abstraction. | ||