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scratch:start [2020/05/18 01:22]
prafull
scratch:start [2020/12/02 01:00] (current)
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 ====== Basic circuits ====== ====== Basic circuits ======
-    - A simple inverter +    - [[tutorial 1 - A simple inverter]] covering (production rules, prs block, defproc incl. in/out, instantiation, aflat and prsim) 
-    - More combinational gates+    - [[tutorial 2 - More combinational gates]]
     - Creating [[namespace|libraries and namespaces]]     - Creating [[namespace|libraries and namespaces]]
       - [[bestpractices|Best practices]] for organizing a complex project       - [[bestpractices|Best practices]] for organizing a complex project
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     - Dual rail logic gates     - Dual rail logic gates
     - Buffers     - Buffers
 +    - QDI ripple-carry adder
 +    - QDI FIFO
  
 ====== Circuit design ====== ====== Circuit design ======
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     - Generating spice [[netlist|netlist]] and simulation with [[https://xyce.sandia.gov/about_xyce/index.html|Xyce]]     - Generating spice [[netlist|netlist]] and simulation with [[https://xyce.sandia.gov/about_xyce/index.html|Xyce]]
     - Spice simulation (details)     - Spice simulation (details)
-    - +    - Reset, power supply, and prs attributes
  
 ====== Physical design ====== ====== Physical design ======
 +    - Configuration file
 +    - Layout generation from netlist, Magic
 +    - DRC, LVP
 +    - Extraction and spice simulation
 +