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scratch:tutorial_1_-_a_simple_inverter [2020/11/02 11:08] – ole | scratch:tutorial_1_-_a_simple_inverter [2020/12/02 06:00] (current) – external edit 127.0.0.1 | ||
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</ | </ | ||
- | These statements are two // | + | These statements are two // |
* The left hand side is a Boolean expression | * The left hand side is a Boolean expression | ||
* The right hand side is a signal transition | * The right hand side is a signal transition | ||
Line 86: | Line 86: | ||
</ | </ | ||
- | the prsim simulator can only read pure production rule files, and not the hierarchical act files we use so to simulate we need to convert our definition. | + | the prsim simulator can only read pure production rule files, and not the hierarchical act files with embedded production rules we wrote before. So to simulate we need to convert our definition |
If the file above is called '' | If the file above is called '' | ||
Line 110: | Line 110: | ||
(Prsim) initialize | (Prsim) initialize | ||
+ | </ | ||
+ | '' | ||
+ | after you entered initialize the sim is set up, but we still want to see what happens so we need to add some '' | ||
+ | < | ||
(Prsim) watch inv.i | (Prsim) watch inv.i | ||
(Prsim) watch inv.o | (Prsim) watch inv.o | ||
+ | </ | ||
+ | we can also use prsim to show us all signals that are 1 or X with '' | ||
+ | < | ||
+ | (Prsim) status 1 | ||
+ | </ | ||
+ | no output but for | ||
+ | < | ||
(Prsim) status X | (Prsim) status X | ||
+ | --------------------------------------- | ||
+ | inv.o inv.i | ||
+ | </ | ||
+ | it shows us that our signals are not set. so lets do this with '' | ||
+ | < | ||
(Prsim) set inv.i 0 | (Prsim) set inv.i 0 | ||
+ | </ | ||
+ | to see what will change in the circuit we now have to let the simulation run a cycle with | ||
+ | < | ||
(Prsim) cycle | (Prsim) cycle | ||
+ | --------------------------------------- | ||
+ | 0 inv.i : 0 | ||
+ | 10 inv.o : 1 [by inv.i:=0] | ||
+ | </ | ||
+ | |||
+ | so the first line '' | ||
+ | the second line '' | ||
+ | |||
+ | the standard gate delay in prsim (from input to output of the inverter) is on default 10 steps thats why the steps advance by 10. | ||
+ | |||
+ | lets also test the other direction: | ||
+ | |||
+ | < | ||
(Prsim) set inv.i 1 | (Prsim) set inv.i 1 | ||
(Prsim) cycle | (Prsim) cycle | ||
+ | --------------------------------------- | ||
+ | 10 inv.i : 1 | ||
+ | 20 inv.o : 0 [by inv.i:=1] | ||
</ | </ | ||
- | '' | + | |
+ | so again the first line '' | ||
+ | and the second line '' | ||
+ | |||
+ | |||
+ | |||
+ | as a summery | ||
One of the useful features of '' | One of the useful features of '' |