Differences

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--- scratch:tutorial_1_-_a_simple_inverter [2020/11/02 07:05]
ole
+++ scratch:tutorial_1_-_a_simple_inverter [2020/12/02 01:00] (current)
@@ Line 31: / Line 31: @@
 </code>
-These statements are two //production rules.// ([[language:langs:prs|prs documentation]]). If you have designed asynchronous circuits, then this terminology should be familiar. A production rule behaves in the following way:
+These statements are two //production rules.// ([[language:langs:prs|prs documentation]]). They are embedded into the ACT hirachy, therefor the file type is act. If you have designed asynchronous circuits, then this terminology should be familiar. A production rule behaves in the following way:
    * The left hand side is a Boolean expression
    * The right hand side is a signal transition
@@ Line 86: / Line 86: @@
 </file>
-the prsim simulator can only read pure production rule files, and not the hierarchical act files we use so to simulate we need to convert our definition.
+the prsim simulator can only read pure production rule files, and not the hierarchical act files with embedded production rules we wrote before. So to simulate we need to convert our definition to plain and flat production rules.
 If the file above is called ''test_inv.act'', a production rule file can be created from the ACT file by:
@@ Line 124: / Line 124: @@
 <code>
 (Prsim) status X
+---------------------------------------
 inv.o inv.i
 </code>
@@ Line 133: / Line 134: @@
 <code>
 (Prsim) cycle
+---------------------------------------
 inv.i : 0
 inv.o : 1  [by inv.i:=0]
@@ Line 139: / Line 141: @@
 so the first line ''0 inv.i : 0'' shows that out set 0 command (''inv.i : 0'') from above was applied at step 0 (''0 in...''),
 the second line ''10 inv.o : 1  [by inv.i:=0]'' shows us that the inverter inverted the input: from left to right at timesept ''10'' the output ''inv.o'' switched to 1 '': 1'', this swich was initated/caused by the input beeing set to 0 ''[by inv.i:=0]''
+the standard gate delay in prsim (from input to output of the inverter) is on default 10 steps thats why the steps advance by 10.
 lets also test the other direction:
@@ Line 145: / Line 149: @@
 (Prsim) set inv.i 1
 (Prsim) cycle
-inv.i : 1
+---------------------------------------
-inv.o : 0  [by inv.i:=1]
+inv.i : 1
+inv.o : 0  [by inv.i:=1]
 </code>
 so again the first line ''10 inv.i : 1'' reads at timesept ''10'' the input ''inv.i'' switched to 1 '': 1''
-and the second line ''20 inv.o : 0  [by inv.i:=1]'' reads at timesept ''20'' the input ''inv.i'' switched to 1 '': 1'' , this switch was initated/caused by the input set to 1 ''[by inv.i:=1]''
+and the second line ''20 inv.o : 0  [by inv.i:=1]'' reads at timesept ''20'' the input ''inv.i'' switched to 0 '': 0'' , this switch was initated/caused by the input set to 1 ''[by inv.i:=1]''