Differences

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--- sim:start [2022/07/17 10:02] – rajit
+++ sim:start [2024/02/27 15:43] (current) – [Components] fabian
@@ Line 1: / Line 1: @@
-====== Namespace sim ======
+====== Simulation library ======
-The ''sim'' namespace contains a collection of process definitions that can be used to create simple test environments for simulation purposes.
+The simulation library is a collection of components which will aid you in testing and verifying your designs. Components in this library are decidedly not synthesizable and should never be included in a final design. A lot of the components use actsim's capability to call external C functions from within CHP code.
-<code act>
+All components of the simulation library can be found within the ''sim'' namespace. There are several sub-namespaces which contain components which fall under the same group. You can access all these components by importing the ''sim'' namespace.
-template<pint W, V>
-defproc source (chan!(int<W>) O);
-</code>
-This creates a data source that has bit-width ''W'', and that repeatedly sends the constant value ''V'' on the output port ''O''.
 <code act>
-template<pbool LOG; pint W>
+import sim;
-defproc sink(chan?(int<W>) I);
 </code>
-This process acts as a data sink; it repeatedly receives ''W''-bit input on the input port ''I''. If the ''LOG'' parameter is set to true, then it also displays the value received using the ''log()'' command.
-<code act>
-template<pint W; pbool REP; pint N; pint data[N]>
-defproc source_seq(chan!(int<W>) O);
-</code>
-This process also provides a ''W''-bit source. Values generated by this source are specified in the ''N''-entry 'data[]'' array. The outputs produced are ''data[0]'', ''data[1]'', ..., ''data[N-1]''. If ''REP'' is set to true, then this sequence is repeated forever.
+===== Components =====
+   * [[sources | Sources]]: Components which emit tokens onto channels; multiple data origins are supported
+   * [[sinks | Sinks]]: Absorbs tokens
+   * [[scoreboards | Scoreboards]]: Advanced form of sink; used for verifying a micro-architecture design against a model or known good output
+   * [[loggers | Loggers]]: Can be fitted onto a channel between two components to log transferred data without being visible to either end
+   * [[ inf_buffer | Infinite capacity buffer]]: Can be used to remove possible timing influences of the simulation harness on the design under test
+   * [[rng | Random number generators]]: Source which outputs random tokens
+   * [[file | File interaction functions]]: Enables basic interactions with data input and output files
+   * [[splitter | Splitter]]: Replicates incoming token onto a specified number of output channels without influencing slack