import "adder.act";
import sim; // import simulation namespace

defproc test()
{
    adder a;
    // The first parameter is the file ID (default name is _infile_.0). 
    // The second parameter is whether the file should be looped.
    // The third parameter is the bit-width.
    sim::file_source<0, false, 32> s1(a.A);
    
    // This could also use a file source
    sim::source_seq<32, false, 3, {7,9,3}> s2(a.B);
    sim::sink<true, // log output
              32  // 32-bit
              > sx(a.C);
 }