import "adder.act";
import sim; // import simulation namespace

defproc test()
{
    adder a;
    // The first parameter is the bitwidth
    // The second parameter is the file ID (default name is _infile_.0). 
    // The third parameter is whether the file should be looped.
    // The fourth parameter is the source ID for logging
    // The fifth parameter specifies if the source should log its output
    sim::source_file<32, 0, false, 0, false> s1(a.A);
    
    // This could also use a file source
    sim::source_sequence<32, 3, {7,9,3}, false, 1, false> s2(a.B);
    sim::sink<32,  // 32-bit
                     0, // sink ID for logging
                     true // log values
              > sx(a.C);
 }