====== Layout configuration options ======
The layout configuration parameters have to be selected by examining the design rule manual for the technology of interest. Since these parameters tend to be covered by NDAs, the ones provided below are for illustration purposes only and don't correspond to any real technology (they are roughly similar to the scalable CMOS rules).
Note that the ''layout.conf'' file is treated specially: all parameters within it are assumed to be within a ''begin layout''/''end'' block.
===== General parameters =====
begin info
string name "scmos"
string date "Created on Feb 26, 2018 by Rajit Manohar"
end
This is a simple information section to provide some information about the design rules and which technology they are for. Note that the ''name'' field should be a string without any whitespace characters.
begin general
real scale 300 # rules use 300nm as one unit
int metals 3 # three metal layers
int dummy_poly 0 # dummy poly
int welltap_adjust 0 # welltap adjustment
end
The scale factor converts the units in the file to nanometers. The number of metals is specified in this section as well. Additionally, a global parameter that specifies the number of dummy polys needed when drawing transistors is also included in this section.
''welltap_adjust'' is a special parameter used in the generation of welltap cells. In some technologies,
the well contact for n-type devices has to be moved down relative to its default generation. The ''welltap_adjust'' is set to the distance the contact for n-type transistor has to be moved down relative to its default location.
==== Range tables ====
Simple drawing rules for a material can be specified using minimum width and minimum spacing rules. This used to be sufficient for older CMOS technologies. More modern technologies have more complex rules, that are of the form: `if some other dimension is in the range [a,b], then the minimum width/spacing/overhang is c'. This can be specified by a tuple (a,b,c). To specify rules of this type, we use integer //range tables//.
Tables of this type will have 2n+1 entries, where n is the number ranges to be specified, with the last entry being the value of c for all other ranges. To specify a collection rules of the type (a0,b0,c0), (b0+1,b1,c1), (b1+1,b2, c2), etc. we assume the ranges cover all possible values of the the 'other dimension.' This means that a0 is implicit---it is the minimum legal value (can be taken as zero if necessary). The table will be specified with entries b0, c0, b1, c1, b2, c2, etc.
For illustration purposes, we know that in some modern technologies, polysilicon overhang over diffusion can depend on the width of the polysilicon drawn.
int_table overhang 8 4 12 6 8
This specifies that: for widths [0,8] the overhang is 4 units; for widths [9,12] the overhang is 6 units; for all other widths, the overhang is 8 units.
==== GDS Layers ====
Although ACT mostly deals with abstract geometry, eventually the design has to be converted into foundry-standard GDS format. To support this, the GDS section is used to specify GDS layer names and the GDS layer numbers for each GDS layer. This section can be omitted if you'd like to stop at abstract geometry, and convert your design to GDS using other mechanisms (e.g. through your own technology file for commercial tools or for open-source layout editors like ''magic'').
begin gds
string_table layers "PO" "OD" "CO" "M1" "M2" "M3"
int_table major 1 2 3 4 5 6
int_table minor 0 0 0 0 0 0
end
This specifies the GDS layer names using ''layers'', and the corresponding major and minor layer number. When the ''gds'' section is specified, all material sections must provide two additional parameters:
* ''gds'', a string table of GDS layers (names) that should be generated for the abstract geometry
* ''gds_bloat'', the amount the geometry should be bloated during layer generation
*
For metal and via templates, the additional information is described in the template section.
===== Base layer material names =====
The next section specifies the names/types for various types of diffusion, transistors, wells, and substrate diffusion.
begin diff
string_table types "svt" # only svt devices
string_table ptype "pdiff" # p diffusion
string_table ntype "ndiff" # n diffusion
string_table pfet "ptransistor" # fets
string_table pfet_well "nwell:nndiff" # well for p-fet, and nplus diff
string_table nfet "ntransistor" # fets
string_table nfet_well ":ppdiff" # no pwell, but pplus diff exists
end
The ''types'' table corresponds to the different types of transistors/diffusion, and hence has to match the ''dev_flavors'' table in the global ACT configuration. Each following table specifies the names of the layout layers in the order specified by the ''types'' table. For wells, each entry corresponds to the well name followed by a colon, and then followed by the substrate diffusion name. If the colon is omitted, the string corresponds to the well name. If there is no well or substrate diffusion, then the empty string can be used. The names ''nndiff'' and ''ppdiff'' are used to indicate nplus diffusion and pplus diffusion, and is only used to draw substrate (well) contacts.
===== Materials for transistors =====
The materials section contains all the information about the materials
that the layout library uses. The names used for the different transistor
types (specified in the ''diff'' section) are used in this section.
In addition, there are built-in names for ''polysilicon'' and each metal
layer (''m'' followed by an integer starting from one). The foundry
technology file contains information that can be
used to map these abstract layers to the correct layer names.
The concrete layers can be generated automatically
from the abstract layers using simple mapping rules. The reason
for doing this is to have a layout generator whose output file can
be easily converted into an input for any layout editor. In the
layout generator directory, we provide a sample translator that creates
a ''magic'' script which can be used to draw all the generated layout
in the ''magic'' VLSI layout editor.
For each diffusion type specified in the header, there must be an
entry that corresponds to the rules used to draw the material. There
are several parameters that can be specified, all integers. The entire
set of parameters are specified within a begin/end section of the
configuration file:
begin materials
begin pdiff
# pdiff parameters go here
end
begin ndiff
# ndiff parameters go here
end
begin ppdiff
# ppdiff parameters go here
end
begin nndiff
# nndiff parameters go here
end
begin ptransistor
# ptransistor parameters go here
end
begin ntransistor
# ntransistor parameters go here
end
begin nwell
# nwell rules go here
end
begin polysilicon
# polysilicon rules go here
end
end
The illustrations below will follow the convention:
{{ :config:definition.svg?400 | Illustration convention}}
==== Diffusion ====
For each type of diffusion, the basic parameters to be specified are:
* ''width'': the minimum width of the material
* ''spacing'': an integer table that specifies the spacing of the diffusion to other diffusions of the same type (''ptype'' or ''ntype''). The order of entries in this table corresponds to the order in the ''ptype''/''ntype'' table specified in the header.
* ''minarea'': minimum area of material
* ''oppspacing'': similar to ''spacing'', except this is the minimum spacing to the opposite type of diffusion.
* ''polyspacing'': spacing to polysilicon
* ''notchspacing'': if the diffusion has a notch, the spacing between the vertical edge of the notch and the edge of the polysilicon
* ''overhang'': a range table that specifies the diffusion overhang depending on the width of the transistor (i.e. polysilicon) it overhangs. This is used for drawing the end of a transistor stack (sometimes called a channel-connected region).
* ''via'' is a section that contains:
* ''edge'': minimum spacing to the edge of the diffusion for a via
* ''fet'': minimum spacing to a transistor from a diffusion via
{{ :config:diffusion.svg?600 | Diffusion design rules}}
==== Transistors ====
For each type of transistor, the basic parameters to be specified are:
* ''width'': this would normally be the width of polysilicon (i.e. the length of the transistor)
* ''spacing'': minimum spacing range table, where the dimension used is the width of the polysilicon used to draw the transistor.
* ''dummy_poly'': used to have a per transistor type dummy poly specifier. This overrides the general dummy poly rule, if per transistor type dummy poly specifiers are needed by the process.
{{ :config:transistor.svg?350 | Transistor design rules}}
==== Wells and ppdiff/nndiff ====
For each type of well, the basic parameters are:
* ''width'': the minimum width of the well
* ''overhang'': minimum overhang of well from diffusion edge
* ''overhang_welldiff'': minimum overhang of well from well diffusion (pplus/nplus) edge; only needed if there is a well diffusion specified
* ''spacing'': a table of spacing rules to wells of the same type
* ''oppspacing'': a table of spacing rules to wells of the opposite type
* ''plug_dist'': the maximum distance of a point in the well to a well plug
{{ :config:well.svg?600 | Well design rules}}
For each type of nplus/pplus diffusion (nndiff and ppdiff), the basic parameters are:
* ''width'': the minimum width of the nndiff/ppdiff region
* ''diffspacing'': spacing between the corresponding diffusion and the nndiff/ppdiff region
* ''spacing'': a table of spacing rules to nndiff/ppdiff of the same type
* ''oppspacing'': a table of spacing rules to nndiff/ppdiff of the opposite type
* ''polyspacing'': the minimum spacing to any polysilicon
* ''minarea'': minimum area of region. For nndiff/ppdiff, this must also satisfy the following constraint: the minarea value divided by the minwidth must satisfy any gridding requirements for the technology (beyond the requirement that all parameters are aligned with the manufacturing grid).
Since nndiff/ppdiff is only drawn for well contacts, the entire region will be within the corresponding well.
{{ :config:plus_diffusion.svg?400 | nplus/pplus diffusion design rules}}
==== Polysilicon ====
All transistors are drawn by polysilicon intersecting with
diffusion. The type of transistor is determined by the type of
diffusion. Polysilicon is the one unusual layer in that it may also
get used for routing, even though its primary purpose is to define
transistors. The polysilicon section has:
* ''width'': minimum width
* ''spacing'': minimum spacing range table, where the dimension used is the width of the polysilicon (i.e. different spacings for different widths). Note that spacing/width here is combined with the spacing/width for the transistor type when drawing transistors.
* ''pitch'': if this is specified, then all polysilicon has to snap to the specified pitch (left edge for vertical drawing, bottom edge for horizontal drawing).
* ''direction'': specify a hard constraint on how polysilicon can be drawn. 0 = no constraint, 1 = vertical only, 2 = horizontal only
* ''minarea'': the minimum area of the material
* ''minjog'': an integer that specifies that if you turn 90 degrees, the minimum amount of material that you have to draw in the new direction. If this is -1, then turns are not allowed.
* ''endofline'': this is the amount one has to extend the end of line for design rule checking.
* ''endofline_width'': this is used to specify the region where the end of line rule is active.
* ''overhang'': a range table that specifies the overhang of poly over diffusion. The range dimension corresponds to the width of the polysilicon/transistor
* ''notch_overhang'': a range table that specifies the overhang over diffusion in the case of a diffusion notch.
* ''via'' is a section that contains:
* ''nspacing'': a spacing table for a poly via to different types of n-type diffusion
* ''pspacing'': a spacing table for a poly via to different types of p-type diffusion
* ''antenna'' is a section that contains any of the following:
* ''ratio'': antenna ratio for this layer (default is to omit this constraint)
* ''diffratio'': antenna ratio when connected to diffusion (default is to omit this constraint)
{{ :config:poly.svg?600 | Poly design rules}}
===== Metal layers =====
Metal layer rules are a subset of the rules used for polysilicon. Essentially they are similar except for the rules related
to diffusion/transistors. Often a technology has many metal layers, but many of the layers have the same design rules. To support this common scenario, we specify metal layers using metal layer templates. Metal layers are referred to using ''m1'', ''m2'', etc. based on the total number of metal layers specified.
begin materials
begin metal
begin 1x
# rules for 1x metal go here
end
begin 2x
# rules for 2x metal go here
end
string m1 "1x"
string m2 "1x"
string m3 "2x"
end
end
The items within the metal specification are:
* ''width'': minimum width range table, where the dimension is the length of the metal (i.e. different widths for different lengths)
* Metal spacing can be specified in a few ways:
* Simple rules can be specified with one parameter
* ''spacing'': minimum spacing range table, where the dimension used is the width of the metal (i.e. different spacings for different widths).
* For more complex cases, we can specify a more complicated set of rules.
* ''spacing'': this is specified as above, and corresponds to the first spacing table.
* ''runlength'': a table specifying the list of parallel run lengths, in ascending order. (0 is not specified, see below)
* ''spacing1'', ''spacing2'', ..., ''spacingk'': k additional range tables for spacing (see below)
* ''runlength_mode'': 0 or 1
* if this is 0, then this corresponds to a standard PARALLELRUNLENGTH specification of spacing rules. These rules are indexed by the width of the largest of the two objects being compared. The value of k is the size of the ''runlength'' table, and each runlength has the corresponding spacing rules. For simplicity, we assume that the last ''spackingk'' table has all the range intervals of all preceding spacing tables.
* if this is 1, then this corresponds to a standard TWOWIDTHS specification of spacing rules. Here we have to look at both widths to index into the table. The value of k is the number of widths in the ''spacing'' table, and each spacing table has to have the same size and width thresholds. In addition, we have parallel run length specifiers (optional) for each spacing table in the ''runlength'' specifier (-1 indicates a missing PRL specifier), so the ''runlength'' table in this case is of size (k+1).
* Influence rules can be specified for spacing rules when two wires are adjacent on two edges
* ''influence'': this is an integer table of size 3*n, where each triplet corresponds to the width, within, and spacing rules (see the LEF/DEF reference).
* ''direction'': specify a hard constraint on how a metal layer can be drawn. 0 = no constraint, 1 = vertical only, 2 = horizontal only
* ''minarea'': the minimum area of the material
* ''minjog'': an integer that specifies that if you turn 90 degrees, the minimum amount of material that you have to draw in the new direction. If this is -1, then turns are not allowed.
* ''endofline'': this is the amount one has to extend the end of line for a metal for design rule checking
* ''endofline_width'': this is used to specify the region where the end of line rule is active.
* ''antenna'' is a section that contains any of the following:
* ''ratio'': antenna ratio for this layer (default is to omit this constraint)
* ''diffratio'': antenna ratio when connected to diffusion (default is to omit this constraint)
Two additional parameters can be specified, which are used during LEF generation for automated routing.
* ''lef_width'': if this is specified, then the LEF drawing rules for the metal layer will use this as the drawing width for routing. If it doesn't exist, then this is set to the minimum width.
* ''pitch'': if this is specified, then all metal tracks are defined to snap to the specified pitch (left edge for vertical drawing, bottom edge for horizontal drawing). If unspecified, this is set to the ''lef_width'' plus minimum spacing.
* The centerline for the routing tracks defined are spaced by the pitch, and the centerline is offset by ''lef_width''/2. Make sure that ''lef_width''/2 is a value that results in edges that lie on the manufacturing grid (defined in the [[config:netlist#LEF/DEF_configuration_options|LEF/DEF configuration section]]). Otherwise, the place and route tools will be very upset.
{{ :config:metal.svg?500 | Metal design rules}}
The example below shows how to specify GDS layer names and bloat for metal 1.
string m1 "1x"
string_table m1_gds "GDS" "LAYER" "NAME" "LIST"
int_table m1_gds_bloat 0 0 0 0
When magic technology files are auto-generted from ''layout.conf'', the standard naming conventions in magic are used (e.g. m1 = first metal layer, m2 = second metal layer, etc). When generating LEF/DEF, it is advisable to use the technology layer names used by the foundry.
string m1_lefname "FoundryM1Name"
This will use ''FoundryM1Name'' in the LEF output produced for cells, even though the magic layout layer name will remain ''m1''.
===== Vias =====
When the layout generator draws a contact between two layers, it
consists of a via plus the two layers being connected. Each layer is
drawn using the minimum via surround rules. One of the complexities of
drawing contacts is that this minimal amount of material by itself may
not satisfy the design rule constraints, because each material might
have minimum area rules, and contacts might have asymmetric material
surround requirements.
There are two basic types of contacts: symmetric and asymmetric
contacts. Both have a minimum via surround requirement in terms of the
materials they connect. In symmetric contacts, that is sufficient to
create the contact. In asymmetric contacts, you also need a larger
minimum surround on two opposite sides of the contact. Technologies
sometimes support both contact types, although the layout generator
currently supports only using one of the two contact types.
Like metal layers, via rules are similar for many different supported
vias; hence, vias are also specified using templates as follows:
begin vias
begin ct_to_active
# rules for drawing connections to active here
end
begin via_small
# rules for small vias
end
begin via_large
# rules for large vias
end
string polysilicon "ct_to_active"
string polysilicon_name "gc"
string ndiff "ct_to_active"
string ndiff_name "gc"
string pdiff "ct_to_active"
string pdiff_name "gc"
# maps for diff/transistor/well/select go here
string m1 "via_small"
string m1_name "v1"
string m1_dstyle "via1arrow"
string m2 "via_large"
string m2_name "v2"
string m2_dstyle "via2"
end
There are three sets of strings associated with each via
* ''m''//n// : this specifies the mapping to the via templates (so ''m1'' points to the template rules for the contact between m1 and m2, etc.)
* ''m''//n//''_name'' : this is the name used when the LEF for the contact is generated. The LEF names will be the name with ''_C'' appended to it to indicate it is a contact
* ''m''//n//''_dstyle'' : this is the additional display style that is used when a ''magic'' technology file is generated from this layout configuration file. This field is optional; when omitted, the additional display style used is ''via''X''arrow''.
A via implicitly has a lower and upper layer that it connects. A via template contains the following rules:
* ''width'': the width of via (assumed to be square and fixed size)
* ''lef_width'': this is the width used for LEF generation. If ''lef_width''/2 is not on the manufacturing grid, then the routing tools will be confused. The default value of this parameter is ''width''.
* ''spacing'': the spacing between vias
* ''surround'' section, containing
* ''up'': minimum surround on the upper layer
* ''asym_up'': minimum surround on two opposite sides; if this is different (and larger) than ''up'', then this corresponds to having an asymmetric contact.
* ''dn'': minimum surround on the lower layer
* ''asym_dn'': similar to ''asym_up'' for the lower layer
* Setting both ''asym_up'' and ''asym_dn'' to zero implies that the vias have symmetric surround, and the ''up'' and ''dn'' parameters are used to determine the surround value. If either of the ''asym'' parameters are non-zero, then we assume that we are using asymmetric vias and the ''asym'' parameters are used.
* ''antenna'' is a section that contains any of the following:
* ''ratio'': antenna ratio for this layer (default is to omit this constraint)
* ''diffratio'': antenna ratio when connected to diffusion (default is to omit this constraint)
* ''generate'' section, used to specify generated vias for wider metal. This contains:
* ''dx'': x-spacing between via centers
* ''dy'': y-spacing between via centers
{{ :config:contact.svg?600 | Via design rules}}
The example below shows how to specify GDS information for the m1 via
string_table m1_gds "V1" "OTHER" "LAYERS"
int_table m1_gds_bloat 0 0 0