====== ACT By Example ======

ACT is a hardware description language that has been influenced more by programming languages developed for software rather than hardware. The key difference between ACT and normal software programming languages is that when "variables" are created, those correspond to hardware components. The other key difference is that ACT can be viewed as a //linking// language, where circuits can be //linked// through connections between their I/O ports. 

ACT supports the description of circuits are multiple levels of abstraction in a unified framework. Details of the language can be found in the [[language:start|detailed language description]]. The examples provided below are a gentler introduction to various language features, and may be easier to follow than the language description itself.

===== Circuit examples =====

ACT can describe circuits are multiple levels of abstraction. At the highest level of abstraction, circuits
are described as message-passing programs in the [[language:langs:chp|CHP language]]. At the lowest digital level of abstraction, circuits are described using [[language:langs:prs|production rules]], a syntax for specifying gates.

ACT provides an integrated simulator [[tools:actsim|actsim]] that can simulate circuits at the different levels of abstraction supported by ACT. In addition, we have an older simulator [[tools:prsim|prsim]] that simulates only gate-level circuits. ACT also has exports to other formats, and these can be used to simulate circuits using third party tools such as [[http://opencircuitdesign.com/irsim/|irsim]] or a SPICE simulator.

  * First-in first-out (FIFO) [[intro_example:chp_fifo|buffer]] in CHP, and [[tools:actsim|actsim]] simulation.
  *An [[intro_example:alu|ALU]] in CHP.
  * A simple [[inverter|inverter]] in PRS, along with a simulation using [[tools:prsim|prsim]] and [[tools:actsim|actsim]].
  * More [[gates|combinational gates]] in PRS, and simulating with [[http://opencircuitdesign.com/irsim/|irsim]].
  * A [[templates|parameterized adder]] using templates
  * Dependent [[template_deps|templates]]
  * Using [[standard_sim|standard testing environments]]
  * More on [[connection_info|connections]] and how they work
  * [[loops|Loops]] and selections
  *Other ways to write the [[intro_example:chp_fifo2|buffer example]]
  * [[assertions|Assertions]] in parameterized definitions
  * [[name_mangling|Expanded names]] in ACT
  * Using [[.pure_struct|pure structures]]
  * Defining [[.operators|operators]]

===== Organizing your design =====

Any complex design contains a large number of circuit elements, and the design is typically 
hierarchical with multiple levels of hierarchy. ACT provides the notion of [[language:namespaces|namespaces]] to help with design organization and re-usability.

  * Creating [[namespace|libraries and namespaces]]
  * Organizing your [[files|files]]
  * Tracking [[dependencies|dependencies]] between ACT files


===== Low-level circuit design and SPICE simulation =====

So far we have learned how to describe a circuit in ACT, simulate using actsim, prsim and irsim. Now, we will move on to the next stage i.e. designing CMOS circuits from ACT description. The process of designing circuit often starts with creating a spice netlist to simulate transistor-level circuit behavior. In order to generate a spice netlist, ACT requires some technology-dependent information and information to understand designer’s intent. We use configuration files to provide such information. For more information on configuration files, see [[config:start|ACT configuration files]]

The configuration files are saved in ''$ACT_HOME/conf/<technology>/'' directory. The default technology is called ''generic'', and the default configuration options are in ''global.conf''. It is possible to save technology specific configuration for each tool in a separate configuration file. For example, ''prs2net.conf'' for configuration related to netlist generator and ''layout.conf'' for layout parameters.

   * Specifying transistor [[sizing|sizes]] for CMOS implementation
   * Generating spice [[netlist|netlist]] and simulation with [[https://xyce.sandia.gov/about_xyce/index.html|Xyce]]
   * [[name_mangling|Name mangling]] in ACT
===== External tools =====

ACT can export circuits into industry-standard formats like SPICE, Verilog netlists, and LEF/DEF. This functionality can be used to export designs from ACT into commercial tools.

   * Importing asynchronous circuits into [[cadence_import|Cadence Virtuoso]].