====== The ACT VLSI Design Tools ======

Welcome to the Wiki for the ACT suite of VLSI design tools. ACT is an **A**synchronous **C**ircuit **T**oolkit which has been built from scratch to support the design and implementation of asynchronous logic. While that is the main goal, some of the tools we have developed have also been used for designing synchronous logic. These tools have been developed primarily by [[http://csl.yale.edu/~rajit/|Rajit Manohar]] and his [[http://avlsi.csl.yale.edu/|research group]], and have a long [[history:|history]].

When an existing open-source tool used by mainstream chip designers can be re-purposed for asynchronous design without major issues (in terms of functionality as well as error-prone behavior), we re-use it. Examples include layout editors (e.g. ''magic''), switch-level simulators (e.g. ''irsim''), and analog simulators (e.g. ''Xyce'').
===== Asynchronous design =====

  * [[tutorial:|Tutorials and class materials]]
  * [[asic:start|ACT ASIC flow]]

===== Installation =====

If you are interested in building the tools from scratch:

      * [[install_actflow|actflow]]: use this if you want the full set of tools.
      * [[install|ACT]]: use this if you only want the core language and some basic tools for custom circuit design. The [[install_actflow|actflow build]] installs this repository as well.

We also have a [[summer2024:dockersetup|docker container]] that contains the tools, if you'd like to try them out without installing them on your system.
===== ACT language =====

The ACT language combined with a set of configuration files are used when designing circuits. The configuration files control some basic ACT behavior, and also include technology-specific information (e.g. what is the feature size, what are the transistor types available in the technology, etc.)
 
  * [[language:|Language reference]], and a [[language:migrate|migration guide]] from the older version of ACT.
  * [[config:|ACT configuration files]] needed for a new technology.
  * [[config:runtime|ACT runtime configuration]], used to adjust the operation of the core ACT library and/or passes.
  * [[history:|Language history/lineage]]

===== ACT library =====

In addition to the core language, we also provide some standard ACT libraries that include common definitions/etc. for designing asynchronous circuits.

  * [[stdlib:|Standard library]]
  * [[sim:|Simulation library]], installed together with [[tools:actsim|actsim]]; It provides tools for simulation and verification

For those interested in writing tools, we have some documentation available for the core ACT library and data structures.

  * [[http://avlsi.csl.yale.edu/act_docs/|Using the ACT library]] (work in progress!)
  * [[guide:|Guide to using ACT data structures]]
  * [[guide:makefile|Guide to using the standard Makefiles in ACT]]
===== Tools =====

  * [[stdoptions:|Command-line options]] and environment variables that are common for all core ACT tools
  * [[tools:|Individual tools]]
  * [[asic:start|ASIC flow]]


A summary of the ACT tools for custom circuit design and the plan for future tools is available:

Rajit Manohar. {{ ::gomactech2019.pdf |An Open-Source Design Flow for Asynchronous Circuits}}. //Government Microcircuit Applications and Critical Technology Conference//, March 2019.

If you use the ACT tools for a publication, we would appreciate it if you could cite the following overview [[https://ieeexplore.ieee.org/abstract/document/9321547|paper]].

Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali. An Open-Source EDA Flow for Asynchronous Logic. IEEE Design & Test, Volume 38, Issue 2, pages 27-37, April 2021. 
DOI: 10.1109/MDAT.2021.3051334.


For analog circuit simulation, we primarily use the open-source [[https://github.com/Xyce/Xyce|Xyce]] simulator from Sandia Labs.

===== Community =====

We have a [[http://mattermost.com|Mattermost]] site for users of the ACT tools. Mattermost is an open-source slack alternative. If you are interested in an account, you can [[https://avlsi.csl.yale.edu:8000/signup_user_complete/?id=h8ir9yj4yj8iixm9jq5skh1ima|sign up]]. If you have trouble signing up, please contact [[http://csl.yale.edu/~rajit|Rajit Manohar]].