====== ASYNC 2026 Summer School ======

The 3rd edition of the ASYNC Summer school will be co-located directly before the conference
(June 1-2 2026) as a hybrid event at DTU in Lyngby, Denmark.

The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools.

======= Registration =======

[[https://www.conferencemanager.dk/async2026 | Please sign up here]], the online participation is free, onsite fee is 450 DKK (~60 EUR) and covers lunch, drinks and snacks during the summer school.

For online participation you will receive a zoom link a few days before the summer school and for the onsite location information please see the [[https://asyncsymposium.org/async2026/venue/|ASYNC Symposium website]]


===== Design tools =====

**ACT tools.** We have pre-installed tools in a multi-platform Docker image (linux/arm64 and linux/amd64) using Ubuntu Linux that is accessible through docker hub. The standard way we use this image is [[summer2024:dockersetup|detailed here]]. You can also install the ACT tools from source using the instructions on [[https://github.com/asyncvlsi/actflow/|Github]].((In addition to the ACT tools, the docker image includes binaries for ''magic'', ''irsim'', ''yosys'', and ''Xyce'' (Xyce installed using a [[https://github.com/asyncvlsi/xyce_build/|Github repo that includes dependencies]]), and SPICE models and an irsim parameter file for the  Skywater 130 open-source PDK.)) Documentation is available on [[https://avlsi.csl.yale.edu/act/|this site]] as well.

**Workcraft.** Packages for Workcraft are available on [[https://github.com/workcraft/workcraft/releases/|Github]], with additional [[https://workcraft.org|documentation]] available as well.

====== Sessions ======

The schedule for the two days will follow the template of the first day of the [[https://asyncsymposium.org/async2026/program/|program]]. We will start at 9am
and conclude at 4:30pm. All times are local time in Denmark.

===== Session 1: Behavioral design =====

**Monday, June 1 morning**

This session covers the abstractions used for the behavioral description of asynchronous circuits, and how one can use simulation at this level of abstraction to test the functionality of an asynchronous design.
   * Overview of summer school + introduction to async
   * Behavioral design with message-passing
   * Dataflow Design

^ Time ^ Topic ^  Speaker(s) ^ Video ^
| 9:00 AM | Welcome |||
| 9:10 AM | Summer school overview | Rajit Manohar |  {{ :summer2026:01_introduction.pdf |pdf}} |
| 9:30 AM | Behavioral description: message-passing models | Rajit Manohar | {{ :summer2026:02_behavior.pdf |pdf}} |
| 10:45 AM | Coffee break |||
| 11:00 AM | Dataflow models | Jens Sparsø  | {{ :summer2026:dataflow-async26-v2.pdf |pdf}} |
| 12:10 PM | Lunch break |||

===== Session 2: From Behavior to gates  =====

**Monday, June 1 afternoon**

This session covers systematic techniques to translate the detailed signal-level description of an asynchronous computation into gates.

   * Handshake Protocols
   * Synthesis and Cells
   * Syntax Directed Translation

^ Time ^ Topic ^  Speaker(s) ^ Video ^
| 1:10 PM | Handshake protocols | Rajit Manohar | {{ :summer2026:04_handshake_protocol.pdf |pdf}}|
| 1:30 PM | Gate-level models | Rajit Manohar |  {{ :summer2026:05_gates.pdf |pdf}} |
| 1:45 PM | From dataflow to gates | Montek Singh | {{ :summer2026:montek-async2026-mousetrap.pdf |pdf}} |
| 2:45 PM | From CHP to gates | Rajit Manohar | {{ :summer2026:07_chp_to_gates.pdf |pdf}}  |
| 3:00 PM  | Coffee break |||
| 3:30 PM | CHP to gates wrap-up; Non-determinism | Rajit Manohar | {{ :summer2026:08_nondet.pdf |pdf}} |
| 4:30 PM | Social Event with Pizza and Drinks at DTU |||
===== Session 3: Physical design =====

**Tuesday, June 2 morning**

This session covers mapping a gate-level description of a design into a physical implementation.
   * Timing and Static timing analysis
   * Cell mapping
   * Place and Route

^ Time ^ Topic ^  Speaker(s) ^ Video ^
| 9:00 AM | Timing constraints | Rajit Manohar | {{ :summer2026:10_timing.pdf |pdf}} |
| 9:30 AM | ASIC implementation flow I | Ole Richter & Rajit Manohar| {{ :summer2026:async-backend.pdf |pdf}} |
| 10:45 AM | Coffee break |||
| 11:00 AM | ASIC implementation flow II | Ole Richter & Rajit Manohar | (pdf continued) | 
| 12:10 PM | Lunch break |||

===== Session 4: Customizing Circuits =====

**Tuesday, June 2 afternoon**

We will include special topics, and close out with a social event in the evening.

^ Time ^ Topic ^  Speaker(s) ^ Video ^
| 1:10 PM | Petri net primer | Alex Yakovlev | {{ :summer2026:petri_nets_primer_-_async_summer_school_2026_-_yakovlev.pdf |pdf}}|
| 2:00 PM | Controller design using Petri nets | Alex Yakovlev | {{ :summer2026:async_school_2026_-_petri_nets_-_yakovlev.pdf |pdf}} |
| 3:00 PM  | Coffee break |||
| 3:30 PM | Custom circuit implementation | Rajit Manohar | (live demo) |
| 4:30 PM | End of day ||