magic, irsim, yosys, and Xyce (Xyce installed using a Github repo that includes dependencies), and SPICE models and an irsim parameter file for the Skywater 130 open-source PDK.The 3rd edition of the ASYNC Summer school will be co-located directly before the conference (June 1-2 2026) as a hybrid event at DTU in Lyngby, Denmark.
The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools.
Please sign up here, the online participation is free, onsite fee is 450 DKK (~60 EUR) and covers lunch, drinks and snacks during the summer school.
For online participation you will receive a zoom link a few days before the summer school and for the onsite location information please see the ASYNC Symposium website
ACT tools. We have pre-installed tools in a multi-platform Docker image (linux/arm64 and linux/amd64) using Ubuntu Linux that is accessible through docker hub. The standard way we use this image is detailed here. You can also install the ACT tools from source using the instructions on Github.1) Documentation is available on this site as well.
Workcraft. Packages for Workcraft are available on Github, with additional documentation available as well.
The schedule for the two days will follow the template of the first day of the program. We will start at 9am and conclude at 4:30pm. All times are local time in Denmark.
Monday, June 1 morning
This session covers the abstractions used for the behavioral description of asynchronous circuits, and how one can use simulation at this level of abstraction to test the functionality of an asynchronous design.
Monday, June 1 afternoon
This session covers systematic techniques to translate the detailed signal-level description of an asynchronous computation into gates.
| Time | Topic | Speaker(s) | Video |
|---|---|---|---|
| 1:10 PM | Handshake protocols | Rajit Manohar | |
| 1:30 PM | Gate-level models | Rajit Manohar | |
| 1:45 PM | From dataflow to gates | Montek Singh | |
| 2:45 PM | From CHP to gates | Rajit Manohar | |
| 3:00 PM | Coffee break | ||
| 3:30 PM | CHP to gates wrap-up; Non-determinism | Rajit Manohar | |
| 4:30 PM | Social Event with Pizza and Drinks at DTU | ||
Tuesday, June 2 morning
This session covers mapping a gate-level description of a design into a physical implementation.
Tuesday, June 2 afternoon
We will include special topics, and close out with a social event in the evening.
magic, irsim, yosys, and Xyce (Xyce installed using a Github repo that includes dependencies), and SPICE models and an irsim parameter file for the Skywater 130 open-source PDK.