FPGA modeling

ACT is used to describe asynchronous circuits. Mainstream FPGAs from Xilinx, Altera, etc. don't support asynchronous logic synthesis. There have been many point solutions developed by different research groups to map specific asynchronous circuit structures to Xilinx/Altera FPGAs. The mapping approach is usually tailored both to the FPGA tool set and the asynchronous circuit family being mapped.

To avoid this, we take a different approach. Instead running the circuit asynchronously on the FPGA, we instead view the FPGA as a hardware-accelerated simulator. The mapping converts the ACT implementation into a synchronous simulation model (synthesizable Verilog) that can then be directly mapped to any FPGA without any special mapping requirements. We have developed two tools for this purpose:

1. prs2fpga, that maps a production rule level design to a clocked simulation model, and
2. chp2fpga, that maps a CHP-level design to a clocked simulation model.

Both of these tools are part of the actflow install.

We normally use chp2fpga as this results in the best simulation performance. To get started with chp2fpga, there is a nice tutorial available that was created by one of the users of the ACT tools.

For the FPGA mapping, channels in CHP are implemented with a standard clocked ready/valid protocol. Details are in the papers below.

To understand how the tools work, there are two papers that describe the methodology implemented by these tools:

• Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452–3465 (TCAD), October 2022.
• Ruslan Dashkin and Rajit Manohar. Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(4):1516-1528 (TCAD), April 2025.