Layout Generation

ACT provides support to create new cells, as this may be necessary for certain asynchronous circuit families. This requires a complete layout configuration file that contains design rules.

Currently ACT does not produce fully routed cells. Instead, cell generation proceeds in two phases:

1. Layout for diffusion and polysilicon is generated with labels attached. This layout follows the design rules contained in the ACT layout configuration file. The layout is generated using .rect file syntax (shown below).
   • The .rect file can be easily converted to scripts for your preferred layout editor. An example where a Tcl script for the magic VLSI layout editor can be generated from a .rect file is distributed with the layout repository (part of the actflow distribution), and is called mag.pl.
   • The layout editor is used to complete the layout of the cell.
   • A new .rect file is generated from the layout editor that includes all the changes made (metal layers, etc.) when the cell was drawn. A sample script that does this for the magic VLSI layout editor that is part of the layout repository is mag2rect.py.
2. When .rect files (that correspond to the finished cells) for a cell is available in the cell rect search path, ACT will read them in instead of generating the unrouted cells.

ACT also generates the LEF for each cell along with the technology LEF. When the unrouted cells are used, ACT uses dummy pin locations for this purpose. Once the cell is routed (step 2), the generated LEFs will includes pin information, obstacles, etc. that is suitable for use in the rest of the place and route flow.

.rect files can be converted to/from magic layer types as well as to/from gds layer types. The details of the ..rect file format converts the syntax as well as conversion methods.