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amc:start [2019/05/08 11:32]
samira [AMC Characterization and Functionality Verification]
amc:start [2020/12/02 01:00] (current)
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-In //example_config.py//  file you can specify the following parameters:+In //example_config.py//  file you can specify the following parameters: (//example_config_scn3me_subm.py// is included in git repo for 0.5um technology)
  
 <code> <code>
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 # Bank orientations (orientation of inner-banks and outer-banks).  # Bank orientations (orientation of inner-banks and outer-banks). 
 # Acceptable tuple values are (("H", "H"), (("V", "H"), (("H", "V"), or (("V", "V") # Acceptable tuple values are (("H", "H"), (("V", "H"), (("H", "V"), or (("V", "V")
-bank_orientation = ("V", "H")+bank_orientations = ("V", "H")
  
 # Output directory for the results.  # Output directory for the results. 
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 # Output file name # Output file name
-output_name = "AMC_sram"+name = "AMC_sram"
  
 # Specify the technology name. Default is "scn3me_subm" for SCMOS 0.5um # Specify the technology name. Default is "scn3me_subm" for SCMOS 0.5um
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 # Voltage corners to characterize # Voltage corners to characterize
-supply_voltages = [ 5.0, 4.5 ]+supply_voltages = [5.0, 4.5]
  
 # Temperature corners to characterize # Temperature corners to characterize
-temperatures = [ 25, 125 ]+temperatures = [25, 125]
  
 </code> </code>
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 **Hint:** **Hint:**
  
-AMC characterization relies on SPICE simulations and for large SRAM arrays, characterization is slow. To reduce the characterization time you can trim the SPICE netlist using //AMC/compiler/characterizer/trim_spice.py// file. By timing the SPICE netlist, portions of SRAM array that are not critical during read/write operation will be removed. Trimed netlists can be used for delay calculations. **Do NOT** use trimed netlist for LVS verification or leakage/energy measurement.+AMC characterization relies on SPICE simulations and for large SRAM arrays, characterization is slow. To reduce the characterization time you can trim the SPICE netlist using //AMC/compiler/characterizer/trim_spice.py// file. By timing the SPICE netlist, portions of SRAM array that are not critical during read/write operation will be removed. Trimed netlists can be used for delay calculations. **DO NOT** use trimed netlist for LVS verification or leakage/energy measurement.
 ====== AMC Copyright Notice ====== ====== AMC Copyright Notice ======
  
 ''AMC'' is licensed under GNU General Public License v2.0 ([[https://github.com/asyncvlsi/AMC/blob/master/LICENSE | LICENSE]]). AMC project originated from the OpenRAM code ([[https://github.com/VLSIDA/OpenRAM |OpenRAM]]) version 7b5791b from May 9, 2018, developed by Matthew Guthaus from UC Santa Cruz VLSIDA group as the lead architect and also contributed to by Samira Ataei. AMC developers have made a large number of changes that have to do with changing the memory interface circuits, supporting modern design rules and thin-cell SRAM layout, new partitioning and floorplanning, and different timing and characterization methodology. The organization of the code base mirrors the OpenRAM version 7b5791b. As OpenRAM is under BSD 3-Clause License, portions of code that are derived from OpenRAM remain under BSD license ([[https://github.com/asyncvlsi/AMC/blob/master/LICENSE.OR | LICENSE.OR]]). ''AMC'' is licensed under GNU General Public License v2.0 ([[https://github.com/asyncvlsi/AMC/blob/master/LICENSE | LICENSE]]). AMC project originated from the OpenRAM code ([[https://github.com/VLSIDA/OpenRAM |OpenRAM]]) version 7b5791b from May 9, 2018, developed by Matthew Guthaus from UC Santa Cruz VLSIDA group as the lead architect and also contributed to by Samira Ataei. AMC developers have made a large number of changes that have to do with changing the memory interface circuits, supporting modern design rules and thin-cell SRAM layout, new partitioning and floorplanning, and different timing and characterization methodology. The organization of the code base mirrors the OpenRAM version 7b5791b. As OpenRAM is under BSD 3-Clause License, portions of code that are derived from OpenRAM remain under BSD license ([[https://github.com/asyncvlsi/AMC/blob/master/LICENSE.OR | LICENSE.OR]]).