Timing constraints

Depending on the asynchronous circuit family used, the correct operation of a design may require certain timing constraints to be satisfied. ACT provides a mechanism to specify these timing constraints, and Cyclone can check if the constraints are in fact satisfied using delay information from the timing .lib file and extracted parasitic capacitance/resistance values from an industry standard .spef file.

Constraints are specified using timing forks. Timing forks can be used to specify a wide range of timing constraints; in particular, they can be used to specify relative timing constraints commonly used in asynchronous circuits. They are general enough to be able to specify setup and hold time constraints in clocked circuits as well. Details on how timing forks are specified can be found in the description of the spec body.