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asic:timing:start [2024/03/22 16:05] rajit [Creating the timing graph] |
asic:timing:start [2024/03/22 16:06] (current) rajit [Creating the timing graph] |
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| - When the design has user-specified cells/black box cells, then ACT assumes that timing arcs could potentially relate any input pin of the cell to any output pin, and the arcs are computed based on those specified in the '' | - When the design has user-specified cells/black box cells, then ACT assumes that timing arcs could potentially relate any input pin of the cell to any output pin, and the arcs are computed based on those specified in the '' | ||
| - | Delays and transition times are added to the timing graph using information in the '' | + | Delays and transition times are added to the timing graph using information in the '' |
| ^ Command ^ Meaning | ^ Command ^ Meaning | ||
| Line 35: | Line 34: | ||
| | timer: | | timer: | ||
| - | | | + | |
| ==== Reading in parasitics ==== | ==== Reading in parasitics ==== | ||
| ===== Power ===== | ===== Power ===== | ||