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asic:timing:start [2023/11/23 12:15] rajit [Static Timing and Power Analysis] |
asic:timing:start [2024/03/22 16:06] (current) rajit [Creating the timing graph] |
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===== Timing | ===== Timing | ||
- | Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works. | + | Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works. Please read this before proceeding, as it will explain the terminology used as well as what the '' |
* [[asic: | * [[asic: | ||
* [[asic: | * [[asic: | ||
* [[asic: | * [[asic: | ||
+ | |||
+ | Note that timing analysis requires that the design has been mapped to [[asic: | ||
+ | |||
+ | ==== Reading in Liberty files ==== | ||
+ | |||
+ | The following two commands are used to read in the Liberty ('' | ||
+ | |||
+ | ^ Command ^ Meaning | ||
+ | | timer: | ||
+ | | timer: | ||
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+ | |||
+ | ==== Creating the timing graph ==== | ||
+ | |||
+ | There are two ways to create a timing graph: | ||
+ | - When the design is fully specified in ACT and production rules are specified using cells that are auto-extracted by the ACT tools (e.g. using the '' | ||
+ | - When the design has user-specified cells/black box cells, then ACT assumes that timing arcs could potentially relate any input pin of the cell to any output pin, and the arcs are computed based on those specified in the '' | ||
+ | |||
+ | Delays and transition times are added to the timing graph using information in the '' | ||
+ | |||
+ | ^ Command ^ Meaning | ||
+ | | timer: | ||
+ | | timer: | ||
+ | |||
+ | |||
+ | ==== Reading in parasitics ==== | ||
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===== Power ===== | ===== Power ===== |