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--- asic:timing:start [2024/03/21 13:25]
rajit [Creating the timing graph]
+++ asic:timing:start [2024/03/22 16:06] (current)
rajit [Creating the timing graph]
@@ Line 24: / Line 24: @@
 ==== Creating the timing graph ====
-There are two ways to create a timing graph.
+There are two ways to create a timing graph:
+   - When the design is fully specified in ACT and production rules are specified using cells that are auto-extracted by the ACT tools (e.g. using the ''ckt:cell-map'' command), the timing arcs from each cell are computed from the production rules directly. These arcs are checked against the ''.lib'' file, and an error is reported if the timing arc is missing from the ''.lib''.
+   - When the design has user-specified cells/black box cells, then ACT assumes that timing arcs could potentially relate any input pin of the cell to any output pin, and the arcs are computed based on those specified in the ''.lib'' file.
+Delays and transition times are added to the timing graph using information in the ''.lib'' file. Commands to read in ''.lib'' files are:
-=== Which edges should be ticked? ===
+^ Command ^ Meaning  ^
+| timer:lib-read <file> | This command reads in a timing ''.lib'' file, and returns a handle. This handle is used to refer to the information from the ''lib'' file that was read by the timing engine. |
-This is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph.
+| timer:lib-merge <lh> <file> | This command takes an existing lib handle <lh>, and adds the contents of the ''.lib'' file to the handle |
-== Control logic ==
-Let's consider a simple example of a handshake protocol between two processes shown below.
-{{ :asic:timing:tick_eg1a.png?600 |}}
-In this example, the handshake starts with the request going high (''req+''). This means that the ticked edge would be from ''ack-'' to ''req+'', since the ''i''th transition of ''ack-'' results in the ''(i+1)''th transition of ''req+''. Alternatively, the process might reset with ''req'' high (e.g. if the process P1 begins with a token on its output). In this case, the timing graph would have a different edge ticked as shown below.
-{{ :asic:timing:tick_eg1b.png?600 |}}