Synthesis configuration

The synthesis section of the configuration file specifies options for circuit synthesis in general. In particular, it has options for the expression optimizer, which is the interface between the ACT tool-suite and external logic synthesis tools, such as ABC. We use these external tools to perform synthesis of expressions into combinational logic by emitting Verilog files which correspond to a logical expression, running the synthesis tool to get a mapped Verilog file, and converting that back to an ACT netlist.

Most of these options in this file are technology-specific. The configuration file name is expropt.conf. The entire set of parameters are surrounded by begin synth and end.

This section, within a pair of begin liberty and end blocks, contains paths to liberty files for the cells for this particular technology.

string typical "${ACT_HOME}/act/syn/liberty/osu018_stdcells.lib"

This is the path to the liberty file for the typical corner. This is required for logic synthesis with all currently supported logic synthesis tools (ABC, Yosys, Genus). For Yosys and Genus, additional liberty files for the different corners may also be provided.

string max_power "/path/to/file"
string min_delay "/path/to/file"
string max_delay "/path/to/file"

The max_power corner is the liberty file corresponding to the maximum power corner, which is usually the FF, high-temperature corner. The min_delay corner is the liberty file corresponding to the minimum delay corner, which is usually the FF, low-temperature corner.The max_delay corner is the liberty file corresponding to the maximum delay corner, which is usually the SS, high-temperature corner.

This section is within a pair of begin expropt and end blocks and contains options for the expression optimizer.