Synthesis configuration

The synthesis section of the configuration file specifies options for circuit synthesis in general. In particular, it has options for the expression optimizer (expropt), which is the interface between the ACT tool-suite and external logic synthesis tools, such as ABC. We use these external tools to perform synthesis of expressions into combinational logic by emitting Verilog files which correspond to a logical expression, running the synthesis tool to get a mapped Verilog file, and converting that back to an ACT netlist.

Most of these options in this file are technology-specific. The configuration file name is expropt.conf. The entire set of parameters are surrounded by begin synth and end.

This section, within a pair of begin liberty and end blocks, contains paths to liberty files for the cells for this particular technology.

string typical "${ACT_HOME}/act/syn/liberty/osu018_stdcells.lib"

This is the path to the liberty file for the typical corner. This is required for logic synthesis with all currently supported logic synthesis tools (ABC, Yosys, Genus). For Yosys and Genus, additional liberty files for the different corners may also be provided.

string max_power "/path/to/file"
string min_delay "/path/to/file"
string max_delay "/path/to/file"

The max_power corner is the liberty file corresponding to the maximum power corner, which is usually the FF, high-temperature corner. The min_delay corner is the liberty file corresponding to the minimum delay corner, which is usually the FF, low-temperature corner.The max_delay corner is the liberty file corresponding to the maximum delay corner, which is usually the SS, high-temperature corner.

This section is within a pair of begin expropt and end blocks and contains options for the expression optimizer.

int clean_tmp_files 1

This option deletes temporary files that are generated during expression synthesis such as the behavioral Verilog file that is passed in to the synthesis tool, the resultant mapped verilog file, log files etc. Set to 0 to keep these files.

int verbose 1

Defines the output verbosity for expropt. Set to 0 for no output on stdout, 1 for dots, 2 for full dump of commands that are being run internally.

int skip_verification 0

For genus only. Set to 1 to skip verification with lec.

int synthesis_effort 2

For genus only. Set the synthesis effort level: 0 for low, 1 for medium, 2 for high. The default value is 2.

int vectorize_all_ports 0

When the Verilog file is printed out for mapping, variables of bitwidth 1 are printed with as a single wire type, but all larger bitwidths are printed as wire arrays, such as wire [7:0]. This may lead to incompatibility with other tools that use the output of expropt, and expect the ports of the process to always contain arrays of bools and not single bools. Setting this option to 1 will print single wires as wire [0:0] instead.

string driving_cell LATCH

Set the driving cell for static timing analysis of the mapped combinational gate-level netlist.

real default_load 8.7

Set the default load capacitance on the output of a gate, for static timing analysis of the mapped combinational gate-level netlist. The default value is 1.0.

This sub-section (cache) within the expropt section contains the location of the expression caches, which contained mapped verilog netlists corresponding to arithmetic/logic expressions for this technology. There are two cache locations - global and local. The global cache must be set. A typical location would be a folder within your ACT_HOME.

string global "${ACT_HOME}/shared_cache/expropt/generic"

As an example, this is the path to the global cache for the generic technology. The expression optimizer will automatically create subdirectories within this directory for each logic synthesis tool and use the appropriate cache.

string local "~/local_expr_cache/generic"

If the local cache location is specified, then it is used instead of the global cache. To use the global cache, simply leave this string unset (commented out).

int invalidate 0

The invalidate option erases the entire cache for this technology when the expression optimizer starts up.