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--- config:runtime [2023/01/30 19:13]
rajit [Verilog Global Prefix]
+++ config:runtime [2023/04/04 15:59]
rajit [Verilog global signal prefix]
@@ Line 138: / Line 138: @@
 This specifies that a global signal ''foo'' can be accessed from Verilog using ''top.foo''.
+===== External Black Box Support =====
+ACT also provides a mechanism for "black box" modules---components that are defined elsewhere, like external hard macros. We assume that the external specification of the macros includes:
+     * A LEF file, for layout generation, along with bounding box information in the LEF coordinate system
+     * A SPICE file, for circuit simulation
+     * A Verilog file, for Verilog exports
+     * TBD
+A process is treated as a black box if it is defined with an empty body. For example:
+<code act>
+defproc bbproc (bool? A, B, C; bool! D) { }
+</code>
+is interpreted as a black box by default. (Note that there is a configuration parameter that can be used to turn off this behavior, in which case this component will be eventually stripped out of the design since it does not contain any circuit component.)  For this to work correctly, direction flags for ports must be present.
+The location of the LEF/SPICE/Verilog/etc. for the black box must be included in an ACT configuration file using the following configuration section:
+<code>
+begin macros
+    begin <expanded-name>
+      string lef  "lef_file_path"
+      string spice "spice_file_path"
+      string verilog "verilog_file_path"
+      int llx <val>
+      int lly <val>
+      int urx <val>
+      int ury <val>
+     end
+end
+</code>
+The expanded name is the fully expanded name for the process (in this case ''bbproc<>''). The value (llx,lly,urx,ury) are the bounding box coordinates from the LEF.