Differences

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--- config:runtime [2023/01/31 00:13] – [Decomposition passes] rajit
+++ config:runtime [2025/05/27 18:12] (current) – [Verilog global signal prefix] rajit
@@ Line 32: / Line 32: @@
 </code>
 This specifies a limit on array sizes that also have internal sub-connections (i.e. arrays that are not just simple memories, for example). The limit should be increased as needed, but can have a performance impact if you have a very large array with internal sub-connections.
-===== Attributes =====
-ACT supports attributes on both instances and production rules. An ACT instance can be assigned an attribute in the following way:
-<code act>
-bool v @ [attr=0];
-bool w;
-w @ [attr=5];
-</code>
-In these two examples, the signal ''v'' has an attribute called ''attr'' with value ''0'', and signal ''w'' has attribute ''attr'' with value ''5''. These attributes can be inspected by tools. Instead of having a hard-coded set of instance attributes, an ACT configuration file can //specify// the list of supported attributes.
-<code>
-begin act
-string_table instance_attr "i:s:autokeeper" "i:s:iscomb" "i:s:sigtype"
-end
-</code>
-This specifies three instance attributes: ''autokeeper'', ''iscomb'', and ''sigtype''.  In general, an attribute is specified as a string of the form ''//x//://y//://name//''
-  * The first component ''//x//'' can be either ''i'' for an integer attribute, ''b'' for a Boolean attribute, or ''r'' for a real attribute.
-  * The second component ''//y//'' specifies how to unify two attributes (which can happen if two instances with different attributes are connected). Supported methods are
-     * ''s'' : for strict; the two attributes must be equal, otherwise an error is reported.
-     * ''+'' : sum, so the attributes are summed
-     * ''M'' : max, so the maximum value is used
-     * ''m'' : min, so the minimum value is used
-     * ''|'' : or, so a logical OR is used
-     * ''&'': and, so a logical AND is used
-A second set of attributes can be specified per-production rule.
-<code>
-string_table prs_attr "i:s:after" "i:s:keeper" "i:s:iskeeper"
-</code>
-The syntax for these is the same, except the attributes are applied per production rule. These attributes are interpreted by the [[tools:prsim|simulator]] as well as [[tools:netgen|netlist generator]].
@@ Line 127: / Line 93: @@
 </code>
-===== Verilog Global Prefix =====
-Since ACT can refer to global signals, this functionality may be needed when converting ACT files into Verilog netlists. Different systems may have different ways that a user can access signals  starting from the top-level in Verilog.
+===== External Black Box Support =====
+ACT also provides a mechanism for "black box" modules---components that are defined elsewhere, like external hard macros. We assume that the external specification of the macros includes:
+     * A LEF file, for layout generation, along with bounding box information in the LEF coordinate system
+     * A SPICE file, for circuit simulation
+     * A Verilog file, for Verilog exports
+     * TBD
+A process is treated as a black box if it is defined with an empty body. For example:
+<code act>
+defproc bbproc (bool? A, B, C; bool! D) { }
+</code>
+is interpreted as a black box by default. (Note that there is a configuration parameter that can be used to turn off this behavior, in which case this component will be eventually stripped out of the design since it does not contain any circuit component.)  For this to work correctly, direction flags for ports must be present.
+The location of the LEF/SPICE/Verilog/etc. for the black box must be included in an ACT configuration file using the following configuration section:
 <code>
-begin act
+begin macros
-  string global_signal_prefix "top"
+    begin <expanded-name>
+      string lef  "lef_file_path"
+      string spice "spice_file_path"
+      string verilog "verilog_file_path"
+      int llx <val>
+      int lly <val>
+      int urx <val>
+      int ury <val>
+     end
 end
 </code>
-This specifies that a global signal ''foo'' can be accessed from Verilog using ''top.foo''.
+The expanded name is the fully expanded name for the process (in this case ''bbproc<>''). The value (llx,lly,urx,ury) are the bounding box coordinates from the LEF. If some files are unavailable, use "/dev/null" as the file name (on Unix-based systems).
+==== Generalized External Black Box ====
+Sometimes we require a more sophisticated model for an external black box. In particular, we might want to specify internal nodes within the black box so that the timing model for the black box can be made more precise. For this purpose, a more general black box syntax is supported.
+<code act>
+defproc bbproc (bool? A, B, C; bool! D) { bool int1, int2; }
+</code>
+This process will also be treated as a black  box, but with the understanding that there are also internal nodes that might be used to build a more sophisticated timing model.
+A generalized black box body can only contain instances of signals that are of type ''bool''.