Differences

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--- config:runtime [2023/01/30 19:13]
rajit [Decomposition passes]
+++ config:runtime [2023/08/25 09:56] (current)
rajit [External Black Box Support]
@@ Line 127: / Line 127: @@
 </code>
-===== Verilog Global Prefix =====
+===== Verilog global signal prefix =====
 Since ACT can refer to global signals, this functionality may be needed when converting ACT files into Verilog netlists. Different systems may have different ways that a user can access signals  starting from the top-level in Verilog.
@@ Line 133: / Line 133: @@
 <code>
 begin act
-  string global_signal_prefix "top"
+  string global_signal_prefix "top."
 end
 </code>
@@ Line 139: / Line 139: @@
 This specifies that a global signal ''foo'' can be accessed from Verilog using ''top.foo''.
+===== External Black Box Support =====
+ACT also provides a mechanism for "black box" modules---components that are defined elsewhere, like external hard macros. We assume that the external specification of the macros includes:
+     * A LEF file, for layout generation, along with bounding box information in the LEF coordinate system
+     * A SPICE file, for circuit simulation
+     * A Verilog file, for Verilog exports
+     * TBD
+A process is treated as a black box if it is defined with an empty body. For example:
+<code act>
+defproc bbproc (bool? A, B, C; bool! D) { }
+</code>
+is interpreted as a black box by default. (Note that there is a configuration parameter that can be used to turn off this behavior, in which case this component will be eventually stripped out of the design since it does not contain any circuit component.)  For this to work correctly, direction flags for ports must be present.
+The location of the LEF/SPICE/Verilog/etc. for the black box must be included in an ACT configuration file using the following configuration section:
+<code>
+begin macros
+    begin <expanded-name>
+      string lef  "lef_file_path"
+      string spice "spice_file_path"
+      string verilog "verilog_file_path"
+      int llx <val>
+      int lly <val>
+      int urx <val>
+      int ury <val>
+     end
+end
+</code>
+The expanded name is the fully expanded name for the process (in this case ''bbproc<>''). The value (llx,lly,urx,ury) are the bounding box coordinates from the LEF. If some files are unavailable, use "/dev/null" as the file name (on Unix-based systems).
+==== Generalized External Black Box ====
+Sometimes we require a more sophisticated model for an external black box. In particular, we might want to specify internal nodes within the black box so that the timing model for the black box can be made more precise. For this purpose, a more general black box syntax is supported.
+<code act>
+defproc bbproc (bool? A, B, C; bool! D) { bool int1, int2; }
+</code>
+This process will also be treated as a black  box, but with the understanding that there are also internal nodes that might be used to build a more sophisticated timing model.
+A generalized black box body can only contain instances of signals that are of type ''bool''.