Custom Flow

The custom flow is for designing, simulating, and verifying hand-designed/optimized circuits.

In the standard custom circuit flow using ACT, there are two basic parts:

• Circuit design. This is done via text entry using an ACT file. In this file you can specify pull-up and pull-down networks as well as transistor sizes (width/length) and type (e.g. low threshold, high threshold).
  • This circuit can be converted into a spice netlist using the netgen tool for analog simulation. This converts a hierarchical ACT design into a hierarchical spice netlist.
  • This circuit can be simulated using existing switch-level simulators like irsim or cosmos using prs2sim, which converts the hierarchical ACT design into a flat simulation file (.sim and .al) that can be read by irsim/cosmos.
  • Asynchronous gate-level simulation can be done using the prsim tool.

• Circuit layout. We assume that the layout is created using the magic VLSI layout editor.
  • The circuit can be :extracted from from magic to create a .ext file. This contains the layout information and parasitics.
  • Magic also permits the creation of a simulation file using the built-in ext2sim (an external tool in older versions, but a built-in command in version 8.x). This can be simulated using irsim/cosmos as well.
  • The layout can be compared against the circuit design in two ways:
    • The existing open-source gemini tool can be used for strict transistor-level comparison between the .sim file generated from the layout, and the .sim file created from the .act file (prs2sim)
    • The ACT-provided lvp tool can be used to compare that the layout matches the production rules used to specify the logic. This tool does not check width/length of transistors, but rather checks that the gates are logically equivalent. It also requires all signals to be named consistently in the layout and ACT file.