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custom:start [2019/05/05 19:05]
rajit |
custom:start [2020/12/02 01:00]
127.0.0.1 external edit |
| * Circuit layout. We assume that the layout is created using the ''magic'' VLSI layout editor. | * Circuit layout. We assume that the layout is created using the ''magic'' VLSI layout editor. |
| * The circuit can be '':extract''ed from from ''magic'' to create a ''.ext'' file. This contains the layout information and parasitics. | * The circuit can be '':extract''ed from from ''magic'' to create a ''.ext'' file. This contains the layout information and parasitics. |
| * Magic also permits the creation of a simulation file using the built-in ''ext2sim'' (an external tool in older versions. This can be simulated using ''irsim''/''cosmos'' as well. | * Magic also permits the creation of a simulation file using the built-in ''ext2sim'' (an external tool in older versions, but a built-in command in version 8.x). This can be simulated using ''irsim''/''cosmos'' as well. |
| * The layout can be compared against the circuit design in two ways: | * The layout can be compared against the circuit design in two ways: |
| * The existing open-source ''gemini'' tool can be used for strict transistor-level comparison between the ''.sim'' file generated from the layout, and the ''.sim'' file created from the ''.act'' file (''prs2sim'') | * The existing open-source ''gemini'' tool can be used for strict transistor-level comparison between the ''.sim'' file generated from the layout, and the ''.sim'' file created from the ''.act'' file (''prs2sim'') |
| * The ACT-provided ''lvp'' tool can be used to compare that the layout matches the production rules used to specify the logic. This tool does not check width/length of transistors, but rather checks that the gates are logically equivalent. It also requires all signals to be named consistently in the layout and ACT file. | * The ACT-provided ''lvp'' tool can be used to compare that the layout matches the production rules used to specify the logic. This tool does not check width/length of transistors, but rather checks that the gates are logically equivalent. It also requires all signals to be named consistently in the layout and ACT file. |
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