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history:start [2023/02/26 08:43] rajit |
history:start [2024/03/26 06:14] (current) rajit |
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====== Language history ====== | ====== Language history ====== | ||
- | This is a rough chronology of the development/ | + | This is a rough chronology of the development/ |
* 1975 E.W. Dijkstra' | * 1975 E.W. Dijkstra' | ||
Line 10: | Line 10: | ||
Language development: | Language development: | ||
- | * ~1991 (?), a language for hierarchical production rules was developed at Caltech (A.J. Martin' | + | * ~1991 (?), a language for hierarchical production rules was developed at Caltech (A.J. Martin' |
< | < | ||
define prs (a)f() | define prs (a)f() | ||
Line 19: | Line 19: | ||
cell (_)f() | cell (_)f() | ||
</ | </ | ||
- | * 1995, a new CAST language ({{ : | + | * 1995, a new CAST language ({{ : |
+ | < | ||
+ | define f (node a) | ||
+ | { node p, q; | ||
+ | prs { | ||
+ | p -> q+ | ||
+ | } | ||
+ | a = p; | ||
+ | } | ||
+ | f(); | ||
+ | </ | ||
* 1995-1998 CAST was used to implement the [[https:// | * 1995-1998 CAST was used to implement the [[https:// | ||
* ~1998 Andrew Lines and Uri Cummings from Martin' | * ~1998 Andrew Lines and Uri Cummings from Martin' | ||
Line 35: | Line 45: | ||
* 1/2019, first [[http:// | * 1/2019, first [[http:// | ||
* 4/2019, documentation effort initiated | * 4/2019, documentation effort initiated | ||
- | |||
- | Tool development: | ||
- | |||
- | * 1990-1995, Caltech point-tools for a number of tasks, including cell generation, placement, routing, and simulation. production rule generation, etc. | ||
- | * 1995-1998, Scalability improvements for simulation, and translation of CAST language to interoperate with previous Caltech tools and newly developed tools including layout checks against production rules and a new implementation of SPICE. | ||
- | * 1998-2010?, in-house tools developed by Fulcrum Microsystems | ||
- | * 1999, new implementation of '' | ||
- | * 2005, ACT tools to convert ACT info formats accepted by existing asynchronous design tools | ||
- | * 2008, new co-simulation tools to leverage commercial simulations and integrate them with asynchronous circuit simulation | ||
- | * 2017, new tools effort started | ||
- | * 2020, support for LEF/DEF exports | ||
- | * 2020, first prototype of '' | ||
- | * 2020-2021, external optimization using open-source logic synthesis tools ('' | ||
- | * 2020-2022, placement and routing flow developed | ||
- | * 2020-2022, dataflow synthesis flow developed | ||
- | * 2021-2023, timing-driven flow in development |