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intro_example:cadence_import [2023/12/11 09:39]
ifx_async [Example: FIFO boolean buffer] 		intro_example:cadence_import [2024/03/13 09:50] (current)
ifx_async [Example: FIFO boolean buffer]
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 ====== Introduction ====== ====== Introduction ======
  
-This guide is intended to explain how to export asynchronous circuits designed in ACT and import them in Cadence Virtuoso to simulate their functioning. We would need some steps to get the Verilog netlist and some editing in order to let the netlist be valid and more readable. We will see all these steps referring to one of the most basic circuits starting from its behavioral description. +This guide is intended to explain how to export asynchronous circuits designed in ACT and import them in Cadence Virtuoso to simulate their functioning.  Some steps are needed to get the Verilog netlist and some editing to let the netlist be valid and more readable. These steps are shown referring to one of the most basic circuits starting from its behavioral description. 
  
 ===== Example: FIFO boolean buffer ===== ===== Example: FIFO boolean buffer =====
    
  
-Let´s assume that we are starting from a block already designed and we would like to simulate its functioning in Cadence Virtuoso. In this tutorial we will refer to the one of the most basic circuits: the FIFO boolean buffer. It can be described in ACT using the CHP sub-language as follows:+Consider as a starting point an already designed block, which has to be simulated in Cadence Virtuoso. This tutorial will refer to the one of the most basic circuits: the FIFO boolean buffer. It can be described in ACT using the CHP sub-language as follows:
 <code act fifobool.act> <code act fifobool.act>
 defproc bool_buff (chan?(bool) L; chan!(bool) R) defproc bool_buff (chan?(bool) L; chan!(bool) R)
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 } }
 </code> </code>
-Let´s save it in a file named fifobool.act.+ The file is saved under the name fifobool.act.
  
-The first step consists in the synthesis of the process. This is done with the command **chp2prs**. Basically, chp2prs maps the synthesized processes using the ACT implementation relation and refine { … } body.  It takes as inputs the act file, which contains the CHP description of the circuit, and the name of the top-level process that has to be synthesized, and returns an output file which contains the synthesized design with .act extension.+The first step consists in the synthesis of the process. This is done with the command **chp2prs**. Chp2prs maps the synthesized processes using the ACT implementation relation and refine { … } body.  It takes as inputs the act file, which contains the CHP description of the circuit, and the name of the top-level process that has to be synthesized, and returns an output file which contains the synthesized design with .act extension.
  
-Then: +Thus: 
 <code> <code>
 >chp2prs fifobool.act bool_buff fifobool_chp2prs.act >chp2prs fifobool.act bool_buff fifobool_chp2prs.act
 </code> </code>
  
-We could also add other options to select bundled-data (-b) or to specify a logic optimizator (-o abc). Let´s see the output:+Other options could be added to select bundled-data (-b) or to specify a logic optimizator (-o abc). The output is:
 <code> <code>
 >cat fifobool_chp2prs.act >cat fifobool_chp2prs.act
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 } }
 </code> </code>
-We can see that the names of the synthesized version are prefixed with sdt_ for syntax-directed translation. +The names of the synthesized version are prefixed with sdt_ which stands for syntax-directed translation. 
-Then we have to do the cell mapping, in order to achieve this we have to launch the interact tool in this way:+Then, in order to achieve the cell-mapping the interact tool is launched in this way:
 <code> <code>
 >interact -ref=1  >interact -ref=1 
 </code> </code>
-Note that we could have specified a technology configuration by adding the option **-Ttechname**.  It changes the technology configuration files to techname. This specifies that the config files are in directory $ACT_HOME/conf/techname. [[stdoptions:start|More info here]].+Note that a technology configuration could have been specified by adding the option **-Ttechname**.  It changes the technology configuration files to techname. This specifies that the config files are in directory $ACT_HOME/conf/techname. [[stdoptions:start|More info here]].
  
-If none is specified as in this case, we get the default configuration located at the following path $ACT_HOME/conf/generic/. [[config:start|More info here]].+If none is specified as in this case, the default configuration located at the following path $ACT_HOME/conf/generic/ is automatically selected. [[config:start|More info here]].
  
 The option -ref=1 is used to select the refinement level.  The option -ref=1 is used to select the refinement level. 
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    gac1x0    gac1x0
    </code>    </code>
-Since we started this design without a cell library, this report indicates the list of fresh cells that are needed to implement the design. To see the production rules for each of these cells, a cell namespace file can be saved as follows:+Since this design was started without a cell library, this report indicates the list of fresh cells that are needed to implement the design. To see the production rules for each of these cells, a cell namespace file can be saved as follows:
 <code> <code>
 interact> ckt:cell-save fifobool_cell_export.act interact> ckt:cell-save fifobool_cell_export.act
 </code> </code>
-Finally, we can export a Verilog netlist. The option -nocell is used to avoid cells definition in the netlist.+Finally, a Verilog netlist can be exported . The option -nocell is used to avoid cells definition in the netlist.
 <code> <code>
 interact> ckt:save-vnet -nocell fifobool_verilog_netlist.v interact> ckt:save-vnet -nocell fifobool_verilog_netlist.v
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 [[asic:cells:start|More info here]]. [[asic:cells:start|More info here]].
  
-In order to make the netlist valid we must erase reg and wire definitions, using regex:+In order to make the netlist valid, reg and wire definitions must be erased. It can be done using regex:
   *Replace '^ +reg .+' with ' '    *Replace '^ +reg .+' with ' '
   *Replace '^ +wire .+' with ' '    *Replace '^ +wire .+' with ' '
-We could also make the netlist more readable:+To also make it more readable:
   *Replace '^_0_0' with  ' '    *Replace '^_0_0' with  ' '
   *Replace '^ cell_0_0' with ' '   *Replace '^ cell_0_0' with ' '
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   *Replace '__' with '_'   *Replace '__' with '_'
   *Replace '_syn' with 'syn'   *Replace '_syn' with 'syn'
 +  *Replace '_std' with 'std'
   *Replace '([ \t]*\n){3,}' with ' ' - eliminating empty gaps   *Replace '([ \t]*\n){3,}' with ' ' - eliminating empty gaps
-  *Erase all empty modules.+  *Erase all empty modules (manually).
 Once this is done, the netlist is ready to be imported in Cadence Virtuoso (File -> Import -> Verilog) and should look like this: Once this is done, the netlist is ready to be imported in Cadence Virtuoso (File -> Import -> Verilog) and should look like this:
 <code verilog fifobool_verilog_netlist.v> <code verilog fifobool_verilog_netlist.v>
intro_example/cadence_import.1702305561.txt.gz · Last modified: 2023/12/11 09:39 by ifx_async
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