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intro_example:cadence_import [2023/12/11 10:11] ifx_async [Example: FIFO boolean buffer] |
intro_example:cadence_import [2024/03/13 09:50] (current) ifx_async [Example: FIFO boolean buffer] |
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| Line 17: | Line 17: | ||
| } | } | ||
| </ | </ | ||
| - | Let´s save it in a file named fifobool.act. | + | |
| - | The first step consists in the synthesis of the process. This is done with the command **chp2prs**. | + | The first step consists in the synthesis of the process. This is done with the command **chp2prs**. |
| - | Then: | + | Thus: |
| < | < | ||
| >chp2prs fifobool.act bool_buff fifobool_chp2prs.act | >chp2prs fifobool.act bool_buff fifobool_chp2prs.act | ||
| </ | </ | ||
| - | Other options could be added to select bundled-data (-b) or to specify a logic optimizator (-o abc). However, the output is: | + | Other options could be added to select bundled-data (-b) or to specify a logic optimizator (-o abc). The output is: |
| < | < | ||
| >cat fifobool_chp2prs.act | >cat fifobool_chp2prs.act | ||
| Line 63: | Line 63: | ||
| } | } | ||
| </ | </ | ||
| - | We can see that the names of the synthesized version are prefixed with sdt_ for syntax-directed translation. | + | The names of the synthesized version are prefixed with sdt_ which stands |
| - | Then, in order to achieve the cell-mapping | + | Then, in order to achieve the cell-mapping the interact tool is launched in this way: |
| < | < | ||
| > | > | ||
| Line 70: | Line 70: | ||
| Note that a technology configuration could have been specified by adding the option **-Ttechname**. | Note that a technology configuration could have been specified by adding the option **-Ttechname**. | ||
| - | If none is specified as in this case, it automatically selects | + | If none is specified as in this case, the default configuration located at the following path $ACT_HOME/ |
| The option -ref=1 is used to select the refinement level. | The option -ref=1 is used to select the refinement level. | ||
| Line 100: | Line 100: | ||
| interact> | interact> | ||
| </ | </ | ||
| - | Finally, | + | Finally, a Verilog netlist |
| < | < | ||
| interact> | interact> | ||
| Line 106: | Line 106: | ||
| [[asic: | [[asic: | ||
| - | In order to make the netlist valid, reg and wire definitions must be erased, using regex: | + | In order to make the netlist valid, reg and wire definitions must be erased. It can be done using regex: |
| *Replace '^ +reg .+' with ' ' | *Replace '^ +reg .+' with ' ' | ||
| *Replace '^ +wire .+' with ' ' | *Replace '^ +wire .+' with ' ' | ||
| Line 115: | Line 115: | ||
| *Replace ' | *Replace ' | ||
| *Replace ' | *Replace ' | ||
| + | *Replace ' | ||
| *Replace '([ \t]*\n){3, | *Replace '([ \t]*\n){3, | ||
| - | *Erase all empty modules. | + | *Erase all empty modules |
| Once this is done, the netlist is ready to be imported in Cadence Virtuoso (File -> Import -> Verilog) and should look like this: | Once this is done, the netlist is ready to be imported in Cadence Virtuoso (File -> Import -> Verilog) and should look like this: | ||
| <code verilog fifobool_verilog_netlist.v> | <code verilog fifobool_verilog_netlist.v> | ||