Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
intro_example:cadence_import [2023/12/12 02:11]
ifx_async [Example: FIFO boolean buffer]
intro_example:cadence_import [2024/03/13 09:50] (current)
ifx_async [Example: FIFO boolean buffer]
Line 17: Line 17:
 } }
 </code> </code>
-Let´s save it in a file named fifobool.act.+ The file is saved under the name fifobool.act.
  
-The first step consists in the synthesis of the process. This is done with the command **chp2prs**. Basically, chp2prs maps the synthesized processes using the ACT implementation relation and refine { … } body.  It takes as inputs the act file, which contains the CHP description of the circuit, and the name of the top-level process that has to be synthesized, and returns an output file which contains the synthesized design with .act extension.+The first step consists in the synthesis of the process. This is done with the command **chp2prs**. Chp2prs maps the synthesized processes using the ACT implementation relation and refine { … } body.  It takes as inputs the act file, which contains the CHP description of the circuit, and the name of the top-level process that has to be synthesized, and returns an output file which contains the synthesized design with .act extension.
  
 Thus:  Thus: 
Line 26: Line 26:
 </code> </code>
  
-Other options could be added to select bundled-data (-b) or to specify a logic optimizator (-o abc). Anyway, the output is:+Other options could be added to select bundled-data (-b) or to specify a logic optimizator (-o abc). The output is:
 <code> <code>
 >cat fifobool_chp2prs.act >cat fifobool_chp2prs.act
Line 64: Line 64:
 </code> </code>
 The names of the synthesized version are prefixed with sdt_ which stands for syntax-directed translation. The names of the synthesized version are prefixed with sdt_ which stands for syntax-directed translation.
-Then, in order to achieve the cell-mapping this the interact tool is launched in this way:+Then, in order to achieve the cell-mapping the interact tool is launched in this way:
 <code> <code>
 >interact -ref=1  >interact -ref=1 
Line 100: Line 100:
 interact> ckt:cell-save fifobool_cell_export.act interact> ckt:cell-save fifobool_cell_export.act
 </code> </code>
-Finally, we can export a Verilog netlist. The option -nocell is used to avoid cells definition in the netlist.+Finally, a Verilog netlist can be exported . The option -nocell is used to avoid cells definition in the netlist.
 <code> <code>
 interact> ckt:save-vnet -nocell fifobool_verilog_netlist.v interact> ckt:save-vnet -nocell fifobool_verilog_netlist.v
Line 106: Line 106:
 [[asic:cells:start|More info here]]. [[asic:cells:start|More info here]].
  
-In order to make the netlist valid, reg and wire definitions must be erasedusing regex:+In order to make the netlist valid, reg and wire definitions must be erased. It can be done using regex:
   *Replace '^ +reg .+' with ' '    *Replace '^ +reg .+' with ' '
   *Replace '^ +wire .+' with ' '    *Replace '^ +wire .+' with ' '
Line 115: Line 115:
   *Replace '__' with '_'   *Replace '__' with '_'
   *Replace '_syn' with 'syn'   *Replace '_syn' with 'syn'
 +  *Replace '_std' with 'std'
   *Replace '([ \t]*\n){3,}' with ' ' - eliminating empty gaps   *Replace '([ \t]*\n){3,}' with ' ' - eliminating empty gaps
-  *Erase all empty modules.+  *Erase all empty modules (manually).
 Once this is done, the netlist is ready to be imported in Cadence Virtuoso (File -> Import -> Verilog) and should look like this: Once this is done, the netlist is ready to be imported in Cadence Virtuoso (File -> Import -> Verilog) and should look like this:
 <code verilog fifobool_verilog_netlist.v> <code verilog fifobool_verilog_netlist.v>