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intro_example:gates [2020/05/01 16:34]
rajit
intro_example:gates [2022/05/13 09:18] (current)
rajit
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 The following specifies a number of combinational gates, where the process names correspond to the commonly used names for the gates. The following specifies a number of combinational gates, where the process names correspond to the commonly used names for the gates.
  
-<code>+<code act>
 defproc inverter (bool? i; bool! o) defproc inverter (bool? i; bool! o)
 { {
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 If we wanted to create a two-input and gate, we could simply write: If we wanted to create a two-input and gate, we could simply write:
  
-<code>+<code act>
 defproc and2 (bool? a, b; bool! c) defproc and2 (bool? a, b; bool! c)
 { {
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 This would be accepted by ACT, and the production rule simulator [[tools:prsim|prsim]] can simulate such rules without difficulty. However, a CMOS circuit designer would observe that one cannot implement this directly using a single pull-up and pull-down network in static CMOS. Instead, someone used to circuit design would write: This would be accepted by ACT, and the production rule simulator [[tools:prsim|prsim]] can simulate such rules without difficulty. However, a CMOS circuit designer would observe that one cannot implement this directly using a single pull-up and pull-down network in static CMOS. Instead, someone used to circuit design would write:
  
-<code>+<code act>
 defproc and2 (bool? a, b; bool! c) defproc and2 (bool? a, b; bool! c)
 { {
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 Since we already have defined ''nand2'' as well as ''inverter'', an alternative approach would be to re-use those circuits as follows: Since we already have defined ''nand2'' as well as ''inverter'', an alternative approach would be to re-use those circuits as follows:
  
-<code>+<code act
 defproc and2 (bool? a, b; bool! c) defproc and2 (bool? a, b; bool! c)
 { {
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 In terms of naming, the ports of ''n'' are ''n.a'', ''n.b'', and ''n.c''; similarly the ports for ''i'' are ''i.i'' and ''i.o''. ACT uses the dot as a hierarchy separator. This version of an ''and2'' contains one level of hierarchy. In terms of naming, the ports of ''n'' are ''n.a'', ''n.b'', and ''n.c''; similarly the ports for ''i'' are ''i.i'' and ''i.o''. ACT uses the dot as a hierarchy separator. This version of an ''and2'' contains one level of hierarchy.
  
-ACT provides a very flexible mechanism for connecting signals. The following variants that correspond to the same connections.+ACT provides a very flexible mechanism for connecting signals. The following are variants that correspond to the same connections.
  
-<code>+<code act>
 defproc and2 (bool? a, b; bool! c) defproc and2 (bool? a, b; bool! c)
 { {
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 The ''='' operator is used to connect two variables. Since connections correspond to //aliasing// (once two Booleans are connected, they are the same signal as far as the circuit is concerned). The ''='' operator is used to connect two variables. Since connections correspond to //aliasing// (once two Booleans are connected, they are the same signal as far as the circuit is concerned).
  
-<code>+<code act>
 defproc and2 (bool? a, b; bool! c) defproc and2 (bool? a, b; bool! c)
 { {
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 To simulate a circuit, you need a top-level instance. Here is a small self-contained example. To simulate a circuit, you need a top-level instance. Here is a small self-contained example.
  
-<code>+<code act>
 defproc inverter (bool? i; bool! o) defproc inverter (bool? i; bool! o)
 { {
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 { {
   nand2 n(.a=a, .b=b);   nand2 n(.a=a, .b=b);
-  inverter i(.i=n.c, .o=c);  // note that we don't need the intermediate _c+  inverter i(.i=n.c, .o=c);  // note that we don't need the intermediate name _c
 } }