Differences

This shows you the differences between two versions of the page.

--- language:langs:sizing [2020/05/02 12:12]
rajit
+++ language:langs:sizing [2021/03/07 07:33]
rajit [Low leak addition on channel length]
@@ Line 62: / Line 62: @@
 Specifying sizing for a production rule that has manual sizing specified is a warning; in this case, the sizing directive is ignored.
+===== Specifying flavors and multi-fingered devices =====
 An example of the general form of the sizing directive is:
 <code>
  sizing {
-   out {-5 <lvt;2> , +4 <lvt;2> }
+   out {-5,lvt,2 ; +4,lvt,2 }
  }
 </code>
@@ Line 72: / Line 74: @@
 <code>
 sizing {
-  out {+4<lvt;2> , -5<lvt;2> }
+  out {+4,lvt,2 ; -5,lvt,2 }
 }
 </code>
@@ Line 80: / Line 82: @@
 <code>
 sizing {
-  unit_n 20;
+  unit_n <- 20;
   out {-1};
 }
@@ Line 86: / Line 88: @@
 This says that the unit n-transistor is 20 lambda wide.
+===== Example using implementation relation =====
+The benefits of a sizing body are best illustrated when combined with the implementation relation. Consider the following example:
+<code>
+defproc inv (bool? i; bool! o)
+{
+  prs {
+    i => o-
+  }
+}
+template<pint drive>
+defproc szinv <: inv()
+{
+  sizing {
+     o {-drive}
+  }
+}
+defproc INVX1 <: szinv<1> () { }
+defproc INVX2 <: szinv<2> () { }
+</code>
+This is an example of defining two standard inverters, that correspond to the same logical production rules but having different sizing.
+===== P/N ratios =====
+The default sizing equalizes drive strengths for the pull-up and pull-down network. For gates used in cyclic control logic in asynchronous design, the optimal drive strengths are different. To use the optimal ratio, you can add:
+<code>
+prs {
+  in[1] & in[0] #> out-
+}
+sizing {
+  p_n_mode <- 1; /* this modifies the sizing */
+  out {-1}
+}
+</code>
+The ratio will be computed using parameters in the netlist section of the ACT [[config:netlist|configuration]] file.
+===== Low leak addition on channel length =====
+In some technologies, the minimum length devices have extremely high leakage. To avoid using these, you can specify an adjustment that will be added to the length to avoid this case. This adjustment is only applied to minimum length devices.
+For adding a specified additional length to the minimum length of your transistors, activate ''leak_adjust''.
+<code>
+prs {
+  in => out-
+}
+sizing {
+   leak_adjust <- 1;
+   out{-1}
+}
+</code>
+To configure how much is added add this line to the configuration
+<code>
+# add to length for leakage management [used if l=min length]
+real leakage_adjust 15e-9
+</code>
+The length unit here is absolute (i.e. not scaled), so the amount specified above is 15nm.