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--- language:langs:sizing [2021/03/05 14:38]
ole [P/N ratios]
+++ language:langs:sizing [2021/03/07 07:33]
rajit [Low leak addition on channel length]
@@ Line 116: / Line 116: @@
 ===== P/N ratios =====
-for state holding gates you want to have a different ratio between P and N compared to normal logic gates, to use the optimal ratio.
+The default sizing equalizes drive strengths for the pull-up and pull-down network. For gates used in cyclic control logic in asynchronous design, the optimal drive strengths are different. To use the optimal ratio, you can add:
-for this you can add:
 <code>
@@ Line 126: / Line 124: @@
 }
 sizing {
-  p_n_mode <- 1;
+  p_n_mode <- 1; /* this modifies the sizing */
   out {-1}
 }
 </code>
-that produces a different ratio:
+The ratio will be computed using parameters in the netlist section of the ACT [[config:netlist|configuration]] file.
-<code>
-  prs {
-      ~in[0]<20> & ~in[1]<20> -> out-
-      ~in[0]<30> & ~in[1]<30>  -> out+
-  }
-</code>
+===== Low leak addition on channel length =====
-===== low leak addition on channel length =====
+In some technologies, the minimum length devices have extremely high leakage. To avoid using these, you can specify an adjustment that will be added to the length to avoid this case. This adjustment is only applied to minimum length devices.
-in some technologies you want to additionally have low leakage gates, so gates with longer channel length.
+For adding a specified additional length to the minimum length of your transistors, activate ''leak_adjust''.
-for adding a specified additional length to the minimum length of your transistors, activate leak_adjust.
 <code>
@@ Line 157: / Line 148: @@
 </code>
-that translates to:
+To configure how much is added add this line to the configuration
-<code>
-  prs * {
-       in <10> -> out-
-      ~in <20> -> out+
-  }
-</code>
-to configure how much is added add this line to the configuration
 <code>
@@ Line 173: / Line 155: @@
 </code>
+The length unit here is absolute (i.e. not scaled), so the amount specified above is 15nm.