The spec sublanguage is used to specify properties or requirements for the circuit. A standard spec directive has the following syntax:

spec {
    directive_name (sig1, sig2, ...)
    directive_name (sig1, sig2, ...)
    ...
}

There are four exclusive directives, two for exclusive high and two for exclusive low. The directive

 spec {
   exclhi (a,b)
 }

states that the signals a and b will not be true (high) simultaneously, and this is guaranteed by the production rules in the circuit.

To simplify modeling of arbiters that cannot be modeled purely at the digital level of abstraction, we include a specific directive that we call “make exclusive high”.

spec {
  mk_exclhi(a,b)
 }

This forces the signals a and b to be exclusive high in the digital simulation model.

There are symmetric variations (excllo and mk_excllo) for exclusive low constraints.

The directive rand_init is used to let the simulator know that a signal might be undefined on power-up, but will initialize to either 0 or 1 at random. The directive hazard is used to let the simulator know that a particular signal can have a switching hazard.

Timing constraints in ACT are specified using timing forks. Timing forks are used to specify a point of divergence constraint. The constraint

spec {
  timing a+ : b- < c+
}

states that after a makes a zero-to-one transition, b makes a one-to-zero transition before c makes a zero-to-one transition.